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CGS410 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CGS410
Description  Programmable Clock Generator
Download  18 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CGS410 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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10 Functional Description
The CMOS clock outputs are generated by a phase lock
loop (PLL) The internal voltage controlled oscillator (VCO)
derives a reference frequency from the crystal input (XTLIN)
and produces a synthesized output A programmable 1 to
16 divider and a passthru mux are positioned between the
VCO and clock outputs allowing a wide range of output
frequencies without having to band switch the VCO A load
clock (LCLK) is also available A synchronous LCLK control
simplifies system frame buffer design
With the CGS410 programmed to run in internal LPF mode
no external low pass filter components are required There
are three internal filters If an external loop filter is desired
or if precise LPF parameters are required the CGS410 can
be programmed to use the external filter pin The external
filter requires two capacitors and one resistor No external
devices such as inductors or varactors are necessary Fre-
quency configuration is programmed through the internal N
R P and L dividers and the 3-to-1 MUX
CGS410 Block Diagram
TLF11919 – 2
20 Pin Definitions
Symbol
Pin
IO
Function
AGND
13
S
Analog Ground
This pin serves as the return for the analog circuitry AGND should also serve as
the external filter return reference as sourced by FILTER AGND should be well referenced to
DGND
AVDD
14
S
Analog VDD
This pin sources the internal VCO internal loop filter and charge pump Due to the
sensitive nature of this pin special care should be taken to filter out noise for best performance
AVDD should track DVDD to within g5%
BGND
21
S
Buffer Ground
Output buffer supply return This serves as the return for the CMOS
PCLK and
LCLK outputs Best output performance is obtained when the CMOS
PCLK and LCLK reception
devices are referenced to BGND
BVDD
20
S
Buffer VDD
This positive power supply input sources LCLK CMOS
PCLK and the differential
PCLK output pair Care must be taken to properly bypass this input with BGND
CMOS
PCLK
22
O
CMOS PCLK Output
This single-ended output is typically used to drive devices which require
CMOS input characteristics
CSB
25
I
Clock for Serial Data Input and Output
This input is TTL compatible edge sensitive In the serial
read or write operation the falling edge latches the R
WB and EN states The rising edge
completes the shift and transfer operation
DATA
26
IO
Data InputOutput
This is a bi-directional IO pin used to transfer data in and out of the CGS410
in a serial fashion Data must be valid when each bit is clocked on the rising edge of the CSB input
DATA is TTL compatible for input mode CMOS compatible for output mode
DGND
3
S
Digital Ground
This pin serves as the return path for the internal CGS410 counter circuitry This
input should be well referenced to BGND
3


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