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CD4023BC Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CD4023BC Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 6 page  TLF5956 February 1988 CD4023BMCD4023BC Buffered Triple 3-Input NAND Gate CD4025BMCD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-chan- nel enhancement mode transistors They have equal source and sink current capabilities and conform to standard B se- ries output drive The devices also have buffered outputs which improve transfer characteristics by providing very high gain All inputs are protected against static discharge with diodes to VDD and VSS Features Y Wide supply voltage range 30V to 15V Y High noise immunity 045 VDD (typ) Y Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74LS Y 5V – 10V – 15V parametric ratings Y Symmetrical output characteristics Y Maximum input leakage 1 mA at 15V over full temperature range Connection Diagrams CD4023BMCD4023BC Dual-In-Line Package TLF5956 – 1 Top View CD4025BMCD4025BC Dual-In-Line Package TLF5956 – 2 Top View Order Number CD4023B or CD4025B C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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