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PT7M6314US46D3 Datasheet(PDF) 4 Page - Pericom Semiconductor Corporation |
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PT7M6314US46D3 Datasheet(HTML) 4 Page - Pericom Semiconductor Corporation |
4 / 8 page ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2016-01-0003 PT0196-6 01/15/16 4 PT7M6314US Supervisory Circuit Block Diagram T.C. Reference 4us one-shot Logic Control &Timing Delay Vcc GND 5kΩ RST VCC Resistor Divider MR 63kΩ Function Description Power Monitor A microprocessor’s (µP’s) reset input starts the µP in a known state. Whenever the µP is in an unknown state, it should be held in reset. The supervisory circuits assert reset during power-up and prevent code execution errors during power-down or brownout conditions. On power-up, once Vcc reaches about 1.0V, RST is a guaranteed logic low of 0.4V or less. As Vcc rises, RST stays low. When Vcc rises above the reset threshold VRST, an internal timer releases RST after about 1570ms (PT7M6314USxxD4). RST asserts whenever Vcc drops below the reset threshold, i.e. brownout condition. If brownout occurs in the middle of a previously initiated reset pulse, the pulse continues for at least another 1.6ms or 26ms or 200ms or 1570ms (PT7M6314USxxD4). On power-down, once Vcc falls below the reset threshold, RST stays low and is guaranteed to be 0.4V or less until Vcc drops below 1V. Manual Reset The manual-reset input (MR) allows reset to be triggered by a pushbutton switch. The switch is effectively debounced by the 1.6ms (PT7M6314USxxD1) or 26ms (PT7M6314USxxD2) or 200ms (PT7M6314USxxD3) or 1570ms (PT7M6314USxxD4) reset pulse width. Reset Output: Bi-direction The PT7M6314USxx’s RESET output is designed to interface with µPs that have bidirectional reset pins, such as the Motorola 68HC11. Like an open-drain output, the PT7M6314USxx allows the µP or other devices to pull RST low and assert a reset condition. However, unlike a standard open-drain output, it includes the commonly specified 5k pull-up resistor with a P- channel active pull-up in parallel. This structure can speed the rising edge when the reset condition releases. The reset condition will occur when Vcc drops below the reset threshold, or Manual Reset is set to ground, or RST is pulled down. |
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