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PT7M6315US30D4 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PT7M6315US30D4 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
1 / 6 page ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Supervisory Circuit 2015-09-0002 PT0197-4 09/15/15 1 PT7M6315US Features Highly accurate: 1.5% (25°C) Detect voltage range: 1.8 to 5V in 100mV increments Operating voltage range: 1.0V ~ 5.5V Operating temperature range: -40°C to + 85°C Detect voltage temperature characteristics: 2.5% TYP Output configuration: N-channel open drain Three reset timeout period available: typical 1.6ms for PT7M6315USxxD1; typical 26ms for PT7M6315USxxD2; typical 200ms for PT7M6315USxxD3; typical 1570ms for PT7M6315USxxD4; Description The series are designed to monitor power supplies in µP and digital systems. It provides excellent circuit reliability and low cost by eliminating external components and adjustments, and a debounced manual reset input. This device performs a single function: it asserts a reset signal whenever the VCC supply voltage falls below a preset threshold or whenever manual reset is asserted. Reset remains asserted for an internally programmed interval (reset timeout period) after VCC has risen above the reset threshold or manual reset is deasserted. The PT7M6315USxx are open-drain RESET output. They can be pulled up to a voltage higher than VCC. The serials come with factory-trimmed reset threshold voltages in 100mV increments from 1.8V to 5V. Preset timeout periods of 200ms (typ.) for PT7M6315USxxD3, 1570ms (typ.) for PT7M6315USxxD4, and 26ms for PT7M6315USxxD2 are available. Pin Configuration Pin Description Name Type Description RST I/O Reset Output: RST is asserted when VCC drops below voltage threshold VTH-. Active low. MR I Manual Reset: A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the reset timeout period (tRS) after the reset conditions are terminated. Connect to VCC if not used. GND P Ground VCC P Supply Voltage. 1 2 VCC RST GND 3 4 MR PT7M6315USxxD3F/D4F SOT143-4 |
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