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S6E2HE Datasheet(PDF) 4 Page - SPANSION |
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S6E2HE Datasheet(HTML) 4 Page - SPANSION |
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4 / 163 page  Document Number: 001-98942 Rev.*A Page 4 of 163 S6E2HE Series Clock supervisor reset Clock SuperVisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. External OSC clock failure (clock stop) is detected, reset is asserted. External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-power Consumption Mode Six low-power consumption modes are supported. Sleep Timer RTC Stop Deep standby RTC (selectable from with/without RAM retention) Deep standby stop (selectable from with/without RAM retention) VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. RTC 32 kHz oscillation circuit Power-on circuit Back up register: 32 bytes Port circuit Debug Serial Wire JTAG Debug Port (SWJ-DP) Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Unique ID Unique value of the device (41-bit) is set. Power Supply Three Power Supplies Wide range voltage: VCC = 2.7 V to 5.5 V Power supply for VBAT: VBAT = 2.7 V to 5.5 V |
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