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ADC12H030 Datasheet(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. ADC12H030
Description  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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ADC12H030 Datasheet(HTML) 10 Page - National Semiconductor (TI)

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AC Electrical Characteristics (Continued)
The following specifications apply for V
+ =V
A+=VD+ = +5.0 VDC,VREF+ = +4.096 VDC,VREF−=0 VDC, 12-bit + sign conver-
sion mode, t
r =tf = 3 ns, fCK =fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, fCK =fSK =5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S =25
Ω, source impedance for V
REF+ and VREF
≤ 25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK) acquisition time unless otherwise specified. Bold-
face limits apply for T
A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
EOC Rising Edge
t
ACC
Access Time Delay from
20
50
ns (max)
CS Falling Edge to DO Data Valid
t
SET-UP
Set-Up Time of CS Falling Edge to
30
ns (min)
Serial Data Clock Rising Edge
t
DELAY
Delay from SCLK Falling
0
5
ns (min)
Edge to CS Falling Edge
t
1H,t0H
Delay from CS Rising Edge to
R
L = 3k, CL = 100 pF
40
100
ns (max)
DO TRI-STATE
t
HDI
DI Hold Time from Serial Data
5
15
ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data
5
10
ns (min)
Clock Rising Edge
t
HDO
DO Hold Time from Serial Data
R
L = 3k, CL = 100 pF
25
50
ns (max)
Clock Falling Edge
5
ns (min)
t
DDO
Delay from Serial Data Clock
35
50
ns (max)
Falling Edge to DO Data Valid
t
RDO
DO Rise Time, TRI-STATE to High
R
L = 3k, CL = 100 pF
10
30
ns (max)
DO Rise Time, Low to High
10
30
ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low
R
L = 3k, CL = 100 pF
12
30
ns (max)
DO Fall Time, High to Low
12
30
ns (max)
t
CD
Delay from CS Falling Edge
25
45
ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling
25
45
ns (max)
Edge to DOR Rising Edge
C
IN
Capacitance of Logic Inputs
10
pF
C
OUT
Capacitance of Logic Outputs
20
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+orVD+), the current at that pin should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD =(TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJmax = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
Thermal
Part Number
Resistance
θ
JA
ADC12H030CIWM, ADC12030CIWM
70˚C/W
ADC12H032CIWM, ADC12032CIWM
64˚C/W
ADC12H034CIN, ADC12034CIN
42˚C/W
ADC12H034CIWM, ADC12034CIWM
57˚C/W
ADC12H034CIMSA
97˚C/W
ADC12H038CIWM, ADC12038CIWM
50˚C/W
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