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ADC12H030 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. ADC12H030
Description  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

ADC12H030 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Pin Descriptions (Continued)
is applied to this pin, the rising edge of SCLK
shifts the data on DI into the address regis-
TRI-STATE. With CS low the falling edge of
SCLK shifts the data resulting from the pre-
vious ADC conversion out on DO, with the
exception of the first bit of data. When CS is
low continously, the first bit of the data is
clocked out on the rising edge of EOC (end
of conversion). When CS is toggled the fall-
ing edge of CS always clocks out the first bit
of data. CS should be brought low when
SCLK is low. The falling edge of CS resets a
conversion in progress and starts the se-
quence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely terminated. The
data in the output latches may be corrupted.
Therefore, when CS is brought back low dur-
ing a conversion in progress the data output
at that time should be ignored. CS may also
be left continuously low. In this case it is
imperative that the correct number of SCLK
pulses be applied to the ADC in order to
remain synchronous. After the ADC supply
power is applied it expects to see 13 clock
pulses for each I/O sequence. The number
of clock pulses the ADC expects is the same
as the digital output word length. This word
length can be modified by the data shifted in
on the DO pin. Table 5 details the data
This is the data output ready pin. This pin is
an active push/pull output. It is low when the
conversion result is being shifted out and
goes high to signal that all the data has been
shifted out.
A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table 5
such as 12-bit conversion, 8-bit conversion,
Auto Cal, Auto Zero etc. When this pin is
high the ADC is placed in the read data only
mode. While in the read data only mode,
bringing CS low and pulsing SCLK will only
clock out on DO any data stored in the ADCs
output shift register. The data on DI will be
neglected. A new conversion will not be
started and the ADC will remain in the mode
grammed. Read data only cannot be per-
formed while a conversion, Auto-Cal or
Auto-Zero are in progress.
This is the power down pin. When PD is high
the A/D is powered down; when PD is low
the A/D is powered up. The A/D takes a
maximum of 250 µs to power up after the
command is given.
These are the analog inputs of the MUX. A
channel input is selected by the address in-
formation at the DI pin, which is loaded on
the rising edge of SCLK into the address
register (See Tables 2, 3, 4).
The voltage applied to these inputs should
not exceed V
A+ or go below GND. Exceed-
ing this range on an unselected channel will
corrupt the reading of a selected channel.
This pin is another analog input pin. It is
used as a pseudo ground when the analog
multiplexer is single-ended.
A/DIN1, /DIN2 These are the converter input pins. MUX-
OUT1 is usually tied to A/DIN1. MUXOUT2
is usually tied to A/DIN2. If external circuitry
is placed between MUXOUT1 and A/DIN1,
or MUXOUT2 and A/DIN2 it may be neces-
sary to protect these pins. The voltage at
these pins should not exceed V
+ or go be-
low AGND (see Figure 5).
This is the positive analog voltage reference
input. In order to maintain accuracy, the volt-
age range of V
is 1 V
DC to 5.0 VDC and the voltage at VREF+
cannot exceed V
A+. See Figure 6 for recom-
mended bypassing.
The negative voltage reference input. In or-
der to maintain accuracy, the voltage at this
pin must not go below GND or exceed V
(See Figure 6).
A+, VD+
These are the analog and digital power sup-
ply pins. V
+ and V
+ are not connected
together on the chip. These pins should be
tied to the same power supply and bypassed
separately (see Figure 6). The operating
voltage range of V
A+ and VD+ is 4.5 VDC to
5.5 V
This is the digital ground pin (see Figure 6).
This is the analog ground pin (see Figure 6).

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