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ADC12D040 Datasheet(PDF) 17 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. ADC12D040
Description  Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference and Sample-and-Hold
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12D040 Datasheet(HTML) 17 Page - National Semiconductor (TI)

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Applications Information (Continued)
TABLE 1. Input to Output Relationship —
Differential Input
V
IN+
V
IN−
Binary Output
2’s Complement
Output
V
CM −0.5* VREF
V
CM +0.5* VREF
0000 0000 0000
1000 0000 0000
V
CM −0.25* VREF
V
CM +0.25* VREF
0100 0000 0000
1100 0000 0000
V
CM
V
CM
1000 0000 0000
0000 0000 0000
V
CM +0.25* VREF
V
CM −0.25* VREF
1100 0000 0000
0100 0000 0000
V
CM +0.5* VREF
V
CM −0.5* VREF
1111 1111 1111
0111 1111 1111
TABLE 2. Input to Output Relationship —
Single-Ended Input
V
IN+
V
IN−
Binary Output
2’s Complement
Output
V
CM −VREF
V
CM
0000 0000 0000
1000 0000 0000
V
CM −0.5* VREF
V
CM
0100 0000 0000
1100 0000 0000
V
CM
V
CM
1000 0000 0000
0000 0000 0000
V
CM +0.5* VREF
V
CM
1100 0000 0000
0100 0000 0000
V
CM +VREF
V
CM
1111 1111 1111
0111 1111 1111
The V
IN+ and the VIN− inputs of the ADC12D040 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high. Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702 and the LMH6628 are good amplifiers for
driving the ADC12D040.
The internal switching action at the analog inputs causes
energy to be output from the input pins. As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 33
Ω series resistors at each of the signal
inputs with a 68 pF capacitor across the inputs, as can be
seen in Figure 5 . These components should be placed close
to the ADC because the input pins of the ADC is the most
sensitive part of the system and this is the last opportunity to
filter the input. The 68 pF capacitor is for Nyquist applica-
tions and should be replaced with a 10 pF capacitor for
undersampling applications.
2.0 DIGITAL INPUTS
Digital inputs consist of CLK, OEA, OEB and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 55 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample rate to 100 ksps.
The clock source should be series terminated to match the
source impedance with the characteristic impedance, Z
O,of
the clock line and the ADC CLK pin should be a.c. termi-
nated, near the CLK pin, with a resistor in series with a
capacitor such that the resistor value is equal to the charac-
teristic impedance of the clock transmission line and
where t
PD is the signal propagation rate down the line, L is
the length of the line in inches and Z
O is the characteristic
impedance of the line.
Typical t
PD is about 150 ps/inch for FR-4 board material.
2.2 OEA, OEB
The OEA or OEB pin, when high, puts the output pins into a
high impedance state. When this pin is low the outputs are in
the active state. The ADC12D040 will continue to convert
whether this pin is high or low, but the output can not be read
while the pin is high.
2.3 PD
The PD pin, when high, holds the ADC12D040 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 75 mW
with a 40MHz clock and 40mW if the clock is stopped. The
output data pins are undefined in this mode. Power con-
sumption during power-down is not affected by the clock
frequency, or by whether there is a clock signal present. The
data in the pipeline is corrupted while in the power down
mode.
2.4 OF
The output data format is offset binary when the OF pin is at
a logic low or 2’s complement when the OF pin is at a logic
high.
3.0 OUTPUTS
The ADC12D040 has 24 TTL/CMOS compatible Data Out-
put pins. Valid data is present at these outputs while the OE
and PD pins are low. While the t
OD time provides information
www.national.com
17


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