The following specifications apply for DV

1.4 MHz, unless otherwise specified. Boldface limits apply for T

Symbol

Parameter

Conditions

Typ

Limit

Units

(Note 7)

(Note 8)

(Limits)

t

CSH

CS Hold Time

20

ns (min)

(CS High after RD High, S/H High, or OE Low)

t

WU

Wake-Up Time

1µs

(PD High to First S/H Low)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-

tional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The

guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed

test conditions.

Note 2: All voltages are measured with respect to GND (GND = AGND = DGND), unless otherwise specified.

to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

(PLCC) package is 55˚C/W. In most cases the maximum derated power dissipation will be reached only during fault conditions.

Note 5: Human body model, 100 pF discharged through a 1.5 k

Ω resistor. Machine model ESD rating is 200V.

Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-

ductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: Typicals are at +25˚C and represent most likely parametric norm.

Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 9: Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.

Note 10: Dynamic testing of the ADC12762 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in the

Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.

Note 11: The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.

Note 12: The contributions from the first nine harmonics are used in the calculation of the THD.

Note 13: Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD − 1.76)/

6.02.

Note 14: The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby

current. Some parts may exhibit significantly higher standby currents than the 50 µA typical.

Note 15: Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.

TRI-STATE Test Circuit and Waveforms

DS012811-2

DS012811-3

www.national.com

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