Electronic Components Datasheet Search |
|
PI7C8150BNDE Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation |
|
PI7C8150BNDE Datasheet(HTML) 5 Page - Pericom Semiconductor Corporation |
5 / 107 page PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 5 of 107 April 2015 – Revision 2.1 TABLE OF CONTENTS 1 INTRODUCTION ...............................................................................................................................11 2 SIGNAL DEFINITIONS ....................................................................................................................12 2.1 SIGNAL TYPES ................................................................................................................................12 2.2 SIGNALS .........................................................................................................................................12 2.2.1 PRIMARY BUS INTERFACE SIGNALS ...........................................................................12 2.2.3 CLOCK SIGNALS ................................................................................................................15 2.2.4 MISCELLANEOUS SIGNALS............................................................................................16 2.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS .........................................................17 2.2.6 JTAG BOUNDARY SCAN SIGNALS .................................................................................17 2.2.7 POWER AND GROUND......................................................................................................18 2.3 PIN LIST – 208-PIN FQFP............................................................................................................18 2.4 PIN LIST – 256-BALL PBGA.......................................................................................................20 3 PCI BUS OPERATION ......................................................................................................................22 3.1 TYPES OF TRANSACTIONS ......................................................................................................22 3.2 SINGLE ADDRESS PHASE.........................................................................................................23 3.3 DEVICE SELECT (DEVSEL_L) GENERATION........................................................................23 3.4 DATA PHASE...............................................................................................................................23 3.5 WRITE TRANSACTIONS ...........................................................................................................23 3.5.1 MEMORY WRITE TRANSACTIONS.................................................................................23 3.5.2 MEMORY WRITE AND INVALIDATE .............................................................................24 3.5.3 DELAYED WRITE TRANSACTIONS................................................................................25 3.5.4 WRITE TRANSACTION ADDRESS BOUNDARIES........................................................26 3.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS......................................................26 3.5.6 FAST BACK-TO-BACK TRANSACTIONS ........................................................................26 3.6 READ TRANSACTIONS .............................................................................................................27 3.6.1 PREFETCHABLE READ TRANSACTIONS.....................................................................27 3.6.2 NON-PREFETCHABLE READ TRANSACTIONS...........................................................27 3.6.3 READ PREFETCH ADDRESS BOUNDARIES ................................................................27 3.6.4 DELAYED READ REQUESTS ...........................................................................................28 3.6.5 DELAYED READ COMPLETION WITH TARGET .........................................................29 3.6.6 DELAYED READ COMPLETION ON INITIATOR BUS.................................................29 3.6.7 FAST BACK-TO-BACK READ TRANSACTION ..............................................................30 3.7 CONFIGURATION TRANSACTIONS .......................................................................................30 3.7.1 TYPE 0 ACCESS TO PI7C8150B........................................................................................31 3.7.2 TYPE 1 TO TYPE 0 CONVERSION ...................................................................................31 3.7.3 TYPE 1 TO TYPE 1 FORWARDING ..................................................................................32 3.7.4 SPECIAL CYCLES ..............................................................................................................33 3.8 TRANSACTION TERMINATION...............................................................................................34 3.8.1 MASTER TERMINATION INITIATED BY PI7C8150B ..................................................35 3.8.2 MASTER ABORT RECEIVED BY PI7C8150B .................................................................35 3.8.3 TARGET TERMINATION RECEIVED BY PI7C8150B ...................................................36 3.8.4 TARGET TERMINATION INITIATED BY PI7C8150B...................................................38 4 ADDRESS DECODING......................................................................................................................41 4.1 ADDRESS RANGES ....................................................................................................................41 4.2 I/O ADDRESS DECODING .........................................................................................................41 4.2.1 I/O BASE AND LIMIT ADDRESS REGISTER .................................................................42 4.2.2 ISA MODE............................................................................................................................43 4.3 MEMORY ADDRESS DECODING.............................................................................................43 4.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ..........................44 15-0048 |
Similar Part No. - PI7C8150BNDE |
|
Similar Description - PI7C8150BNDE |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |