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ADC1251 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. ADC1251
Description  Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC1251 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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AC Electrical Characteristics
The following specifications apply for DVCC e AVCC ea50V Vb eb50V tr e tf e 20 ns unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Notes 10 19)
(Limit)
fCLK
Clock Frequency
MHz
05
MHz(min)
60
35
MHz(max)
Clock Duty Cycle
50
%
40
%(min)
60
%(max)
tC
Conversion Time Using WR
27(1fCLK)
27(1fCLK) a 250 ns
(max)
to Start a Conversion
fCLK e 35 MHz AZ e ‘‘1’’
77
795
m
s(max)
fCLK e 175 MHz AZ e ‘‘0’’
154
1565
m
s(max)
tC
Conversion Time Using S H
AZ e ‘‘1’’
34(1fCLK)
34(1fCLK) a 250 ns
(max)
to Start a Conversion
fCLK e 35 MHz AZ e ‘‘1’’
97
995
m
s(max)
tA
Acquisition Time (Note 15)
RSOURCE e 50X
35
35
m
s(min)
tIA
Internal Acquisition Time
7(1fCLK)
7(1fCLK)
(max)
(When Using WR Control Only)
tZA
Auto Zero Time a Acquisition Time
33(1fCLK)
33(1fCLK) a 250 ns
(max)
fCLK e 175 MHz
188
1905
m
s(max)
tD(EOC)L Delay from Hold Command
Using WR Control
200
350
ns(max)
to Falling Edge of EOC
Using S H Control
100
150
ns(max)
tCAL
Calibration Time
1399(1fCLK)
1399 (1fCLK)
(max)
fCLK e 35 MHz
399
400
m
s(max)
tW(CAL)L Calibration Pulse Width
(Note 16)
60
200
ns(min)
tW(WR)L Minimum WR Pulse Width
60
200
ns(min)
tACC
Maximum Access Time
CL e 100 pF
(Delay from Falling Edge of
50
95
ns(max)
RD to Output Data Valid)
t0H t1H
TRI-STATE Control
RL e 1kX CL e 100 pF
(Delay from Rising Edge of
30
70
ns(max)
RD to Hi-Z State)
tPD(INT) Maximum Delay from Falling Edge
100
175
ns(max)
of RD or WR to Reset of INT
tRR
Delay between Successive RD Pulses
30
60
ns(min)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4
The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation a 1 TTL Load on each digital
output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction
temperature) iJA (package junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature
is PDmax e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJmax e 150 C and the typical thermal
resistance (iJA) of the ADC1251 with CMJ BIJ and CIJ suffixes when board mounted is 51 CW
Note 5
Human body model 100 pF discharged through a 15 kX resistor
4


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