IS61DDB44M18A

IS61DDB42M36A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

12/08/2014

12

x18 Write Truth Table

(Use the following table with the Timing Reference Diagram for Truth Table.)

Operation

K (t+1.0)

K (t+1.5)

K (t+2.0)

K (t+2.5)

Write Byte 0

L → H

L

H

D0-8 (t+4.0)

Write Byte 1

L → H

H

L

D9-17 (t+4.0)

Write All Bytes

L → H

L

L

D0-17 (t+4.0)

Abort Write

L → H

H

H

Don't Care

Write Byte 0

L → H

L

H

D0-8 (t+4.5)

Write Byte 1

L → H

H

L

D9-17 (t+4.5)

Write All Bytes

L → H

L

L

D0-17 (t+4.5)

Abort Write

L → H

H

H

Don't Care

Write Byte 0

L → H

L

H

D0-8 (t+5.0)

Write Byte 1

L → H

H

L

D9-17 (t+5.0)

Write All Bytes

L → H

L

L

D0-17 (t+5.0)

Abort Write

L → H

H

H

Don't Care

Write Byte 0

L → H

L

H

D0-8 (t+5.5)

Write Byte 1

L → H

H

L

D9-17 (t+5.5)

Write All Bytes

L → H

L

L

D0-17 (t+5.5)

Abort Write

L → H

H

H

Don't Care

Notes:

1.

For all cases, R/W# needs to be active low during the rising edge of K occurring at time t.

2.

For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and

K#.