Integrated Silicon Solution, Inc.

1

Rev. 0A

03/24/2014

Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest

version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS43R83200F

IS43/46R16160F, IS43/46R32800F

FEATURES

• VDDandVDDQ:2.5V±0.2V

• SSTL_2compatibleI/O

• Double-dataratearchitecture;twodatatransfers

per clock cycle

• Bidirectional,datastrobe(DQS)istransmitted/

received with data, to be used in capturing data

at the receiver

• DQSisedge-alignedwithdataforREADsand

centre-alignedwithdataforWRITEs

• Differentialclockinputs(CKandCK)

• DLLalignsDQandDQStransitionswithCK

transitions

anddatamaskreferencedtobothedgesofDQS

• Fourinternalbanksforconcurrentoperation

• DataMaskforwritedata.DMmaskswritedata

at both rising and falling edges of data strobe

• BurstLength:2,4and8

• BurstType:SequentialandInterleavemode

• ProgrammableCASlatency:2,2.5and3

• AutoRefreshandSelfRefreshModes

• AutoPrecharge

OPTIONS

• Configuration(s):8Mx32,16Mx16,32Mx8

• Package(s):

144BallBGA(x32)

66-pinTSOP-II(x8,x16)and60BallBGA(x8,x16)

• Lead-freepackageavailable

• TemperatureRange:

Commercial(0°Cto+70°C)

Industrial(-40°Cto+85°C)

Automotive,A1(-40°Cto+85°C)

Automotive,A2(-40°Cto+105°C)

8Mx32, 16Mx16, 32Mx8

256Mb DDR SDRAM

PRELIMINARY INFORMATION

MARCH 2014

DEVICE OVERVIEW

ISSI’s256-MbitDDRSDRAMachieveshighspeeddata

transfer using pipeline architecture and two data word

accessesperclockcycle.The268,435,456-bitmemory

arrayisinternallyorganizedasfourbanksof64Mbto

allowconcurrentoperations.ThepipelineallowsRead

and Write burst accesses to be virtually continuous, with

theoptiontoconcatenateortruncatethebursts.The

programmable features of burst length, burst sequence

andCASlatencyenablefurtheradvantages.Thedevice

isavailablein8-bit,16-bitand32-bitdatawordsize

InputdataisregisteredontheI/Opinsonbothedges

ofDataStrobesignal(s),whileoutputdataisreferenced

tobothedgesofDataStrobeandbothedgesofCLK.

CommandsareregisteredonthepositiveedgesofCLK.

AnAutoRefreshmodeisprovided,alongwithaSelf

Refreshmode.AllI/OsareSSTL_2compatible.

KEY TIMING PARAMETERS

Speed Grade

-5

-6

Units

200

167

MHz

167

167

MHz

133

133

MHz

ADDRESS TABLE

Parameter

8M x 32

16M x 16

32M x 8

Configuration

2Mx32x4

banks

4Mx16x4

banks

8Mx8x4

banks

BankAddress

Pins

BA0,BA1

BA0,BA1

BA0,BA1

Autoprecharge

Pins

A8/AP

A10/AP

A10/AP

RowAddress

4K(A0–A11) 8K(A0–A12) 8K(A0–A12)

Column

Address

512(A0–A7,

A9)

512(A0–A8) 1K(A0–A9)

RefreshCount

Com./Ind./A1

A2

4K/64ms

4K/16ms

8K/64ms

8K/16ms

8K/64ms