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LDC1101DRCR Datasheet(PDF) 3 Page - Texas Instruments |
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LDC1101DRCR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 55 page 1 3 SDO/INTB 4 CLKIN SCLK 5 INB 6 INA 7 GND 8 VDD 9 SDI CLDO 10 2 CSB DAP 3 LDC1101 www.ti.com SNOSD01C – MAY 2015 – REVISED FEBRUARY 2016 Product Folder Links: LDC1101 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) P= Power, G=Ground, I=Input, O=Output, A=Analog (2) There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the GND pin of the device. Although the DAP can be left floating, for best performance the DAP must be connected to the same potential as the GND pin of the device. Do not use the DAP as the primary ground for the device. The device GND pin must always be connected to ground. 6 Pin Configuration and Functions DRC Package 10-Pin VSON Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. CLDO 10 P Internal LDO bypassing pin. A 15-nF capacitor must be connected from this pin to GND. CLKIN 2 I External time-base clock Input CSB 5 I SPI CSB. Multiple devices can be connected on the same SPI bus and CSB can be used to uniquely select desired device DAP – – Connect to ground for improved thermal performance(2) GND 8 G Ground INA 7 A External LC tank – connected to external LC tank INB 6 A External LC tank – connected to external LC tank SCLK 3 I SPI clock input SDI 4 I SPI data input – connect to MOSI of SPI master SDO/INTB 1 O SPI data output/INTB – Connect to MISO of SPI master. When CSB is high, this pin is High-Z. Alternatively, this pin can be configured to function as INTB VDD 9 P Power supply |
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