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IS46LR32400G Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS46LR32400G Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
4 / 43 page 4 Rev. 00A | June 2014 www.issi.com - dram@issi.com IS43/46LR32400G Advanced Information Figure2 : Functional Block Diagram Extended Mode Register Self refresh Logic & timer Internal Row Counter Row Pre Decoder Column Pre Decoder Column Add Counter Address Register Mode Register Data Out Control Burst Counter 1Mx32 BANK 1 1Mx32 BANK 0 Memory Cell Array Column Decoders 1Mx32 BANK 2 1Mx32 BANK 3 Write Data Register 2-bit Prefetch Unit DQ0 . . . . . . . DQ31 Data Strobe Transmitter Data Strobe Receiver | | 32 | | | | 64 | | DS DQS0 ~ DQS3 DS X32 X64 PASR Row Active Refresh Column Active Bank Select CAS Latency A0 A1 A11 BA0 BA1 DM0 ~ DM3 /WE /CAS /RAS /CS CKE CK /CK |
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