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IS43LR16800G Datasheet(PDF) 30 Page - Integrated Silicon Solution, Inc |
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IS43LR16800G Datasheet(HTML) 30 Page - Integrated Silicon Solution, Inc |
30 / 43 page 30 Rev. 00A | June 2014 www.issi.com - dram@issi.com IS43/46LR16800G Advanced Information Figure17 : Read Burst terminate (BL=4,8 or 16) Truncated Reads Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure16. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used. A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the n-prefetch architecture). This is shown in Figure (READ to PRECHARGE). Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Figure16 : Random Read access Notes: 1. Dout n or m,p,q = Data-Out from Column n or m,p,q 2. BL=2,4,8,16 (if 4,8 or 16, the following burst interrupts the previous) 3. Reads are to an Active row in any bank. 4. Shown with nominal tAC, tDQSCK and tDQSQ Notes: 1. Dout n = Data-Out from Column n 2. CKE=high 3. Shown with nominal tAC, tDQSCK and tDQSQ Bank a COL m Bank a COL p DOUT p Bank a COL q Bank a COL n READ READ READ NOP NOP READ T0 T1 T2 T3 Address T4 T5 /CLK CLK DQ CL=3 Command DQS Don’t care DOUT n+1 DOUT n DOUT m DOUT m+1 NOP DOUT q DOUT q+1 DOUT p+1 Bank a COL n NOP READ BST NOP NOP T0 T1 T2 T3 Address T4 /CLK CLK DQ CL= 3 Command DQS Don’ t care D OUT n+ 1 DOUT n |
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