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IS43LD16320A Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS43LD16320A Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
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1 / 143 page  Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. 00C 8/11/2014 Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances IS43/46LD16320A IS43/46LD32160A desCRiption The IS43/46LD16320A/32160A is 512Mbit CMOS LPDDR2 DRAM. The device is organized as 4 banks of 8Meg words of 16bits or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits prefetched to achieve very high bandwidth. 512Mb (x16, x32) Mobile LpddR2 s4 sdRAM AdVAnCed inFoRMAtion AUGUst 2014 FeAtURes • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V • High Speed Un-terminated Logic(HSUL_12) I/O Interface • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O) • Four-bit Pre-fetch DDR Architecture • Multiplexed, double data rate, command/ad- dress inputs • Four internal banks for concurrent operation • Bidirectional/differential data strobe per byte of data (DQS/DQS#) • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16) • ZQ Calibration • On-chip temperature sensor to control self re- fresh rate • Partial –array self refresh(PASR) • Deep power-down mode(DPD) • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) options • Configuration: − 32Mx16 (8M x 16 x 4 banks) − 16Mx32 (4M x 32 x 4 banks) Package: − 134-ball BGA for x16 / x32 − 168-ball PoP BGA for x32 keY tiMinG pARAMeteRs AddRess tABLe Speed Grade Data Rate (Mb/s) Write Latency Read Latency tRCD/ tRP -18 1066 4 8 Typical -25 800 3 6 Typical -3 667 2 5 Typical Parameter 16Mx32 32Mx16 Row Addresses R0-R12 R0-R12 Column Addresses C0-C8 C0-C9 Bank Addresses BA0-BA1 BA0-BA1 Refresh Count 4096 4096 Note: Other clock frequencies/data rates supported; please refer to AC timing tables. |
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