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IS25WP080 Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc |
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IS25WP080 Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc |
9 / 112 page IS25WP016/080/040/020 Integrated Silicon Solution, Inc.- www.issi.com 9 Rev. 00A 01/13/2015 For 16-pin SOIC 300mil package with additional RESET# pin option - RESET# pin will be added to another pin without sharing with HOLD# pin (See the Ordering Information for the parts) SYMBOL TYPE DESCRIPTION CE# INPUT Same as the description in previous page SI (IO0), SO (IO1) INPUT/OUTPUT Same as the description in previous page WP# (IO2) INPUT/OUTPUT Same as the description in previous page HOLD# (IO3) INPUT/OUTPUT HOLD#/Serial Data IO (IO3): When the QE bit of Status Register is set to “1”, HOLD# pin is not available since it becomes IO3. When QE=0 the pin acts as HOLD# regardless of the P7 bit of Read Register. The HOLD# pin allows the device to be paused while it is selected. It pauses serial communication by the master device without resetting the serial sequence. The HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin will be at high impedance. Device operation can resume when HOLD# pin is brought to a high state. RESET# INPUT/OUTPUT RESET#: This additional RESET# pin is available only for dedicated parts. The RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. SCK INPUT Same as the description in previous page Vcc POWER Same as the description in previous page GND GROUND Same as the description in previous page NC Unused Same as the description in previous page ADVANCED INFORMATION |
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