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IS31AP2111 Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS31AP2111 Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
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7 / 31 page  IS31AP2111 Integrated Silicon Solution, Inc. – www.issi.com 7 Rev. 0A, 09/10/2014 AC ELECTRICAL CHARACTERISTICS TA=25°C, VCC=24V, VDD = 3.3V, fS = 48kHz, RL=8 Ω with passive LC lowpass filter (L= 22µH, R DC= 0. 12Ω, C=470nF), input is 1kHz sinewave, volume is 0dB unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit PO RMS output power THD+N=0.38%, +8dB volume (Note 2) 20 W THD+N Total harmonic distortion + noise PO = 10W 0.24 % VNO Output noise 20Hz ~ 20kHz (Note 3) 179 µV SNR Signal-to-noise ratio +8dB volume, input level is -9dB (Note 3) 99 dB DR Dynamic range +8dB volume, input level is -68dB (Note 3) 104 dB PSRR Power supply ripple rejection VRIPPLE = 1VRMS at 1kHz -68 dB Channel separation 1W @1kHz -85 dB I2C DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4) Symbol Parameter Standard Mode Fast Mode Unit Min. Max. Min. Max. fSCL Serial-Clock frequency 0 100 0 400 kHz tBUF Bus free time between a STOP and a START condition 4.7 1.3 μs tHD, STA Hold time (repeated) START condition 4.0 0.6 μs tSU, STA Repeated START condition setup time 4.7 0.6 μs tSU, STO STOP condition setup time 4.0 0.6 μs tHD, DAT Data hold time 0 3.45 0 0.9 μs tSU, DAT Data setup time 250 100 ns tLOW SCL clock low period 4.7 1.3 μs tHIGH SCL clock high period 4.0 0.6 μs tR Rise time of both SDA and SCL signals, receiving 1000 20+0.1Cb 300 ns tF Fall time of both SDA and SCL signals, receiving 300 20+0.1Cb 300 ns Cb Capacitive load for each bus line 400 400 pF VNL Noise margin at the low level for each connected device (including hysteresis) 0.1VDD 0.1VDD V VNH Noise margin at the high level for each connected device (including hysteresis) 0.2VDD 0.2VDD V |
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