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IS46TR81280B Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

Part # IS46TR81280B
Description  Programmable CAS Latency
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS46TR81280B Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc

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IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
Integrated Silicon Solution, Inc.
– www.issi.com –
8
Rev. C1
11/12/2014
2.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1.
Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10
ns).
2.
Follow Power-up Initialization Sequence steps 2 to 11.
3.
The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Figure2.1.2 Reset Procedure at Power Stable Condition
2.3 Register Definition
2.3.1 Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by
the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command.
As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized
and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers
can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even
if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must
be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which
means these commands can be executed any time after power-up without affecting the array contents The mode register
set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time
required between two MRS commands shown as below.
Ta
CK,CK#
VDD,VDDQ
RESET#
CKE
CMMAND
BA
ODT
RTT
Tb
T=100nS
Tmin=10nS
T=500µS
tCKSRX
tIS
tIS
tIS
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Tc
Td
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tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
tDLLK
tIS
Valid
Valid
Valid
Valid
MRD
MRD
MRD
MRD
ZQCL
1)
MR2
MR3
MR1
MR0
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Te
Tf
Tg
Th
Ti
Tj
Tk
Note1. From time point “Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
Time
Break
DON’T
CARE
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
1)


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