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SM320VC33GNMM150 Datasheet(PDF) 10 Page - Texas Instruments |
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SM320VC33GNMM150 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 53 page SM320VC33, SMJ320VC33 SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015 www.ti.com 6.6 Timing Requirements for EXTCLK, All Modes see Figure 3 and Figure 4 MIN MAX UNIT F = Fmax, x0.5 and x1 modes 1(1) tr(EXTCLK) Rise time, EXTCLK ns F < Fmax 4(1) F = Fmax, x0.5 and x1 modes 1(1) tf(EXTCLK) Fall time, EXTCLK ns F < Fmax 4(1) x5 mode 21(1) tw(EXTCLKL) Pulse duration, EXTCLK low x1 mode 6(1) ns x0.5 mode 4(1) x5 mode 21(1) tw(EXTCLKH) Pulse duration, EXTCLK high x1 mode 5(1) ns x0.5 mode 4(1) x5 PLL mode 40%(1) 60%(1) tdc(EXTCLK) Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)] x1 and x0.5 modes, F = max 45% 55% x1 and x0.5 modes, F = 0 Hz 0%(1) 100%(1) x5 mode 66.7(1) 200(1) tc(EXTCLK) Cycle time, EXTCLK x1 mode 13.3 ns x0.5 mode 10(1) x5 mode 5(1) 15(1) Fext Frequency range, 1 / tc(EXTCLK) x1 mode 0 75 MHz x0.5 mode 0(1) 100(1) (1) Not production tested 6.7 Timing Requirements for Memory Read/Write for STRB see Figure 5 through Figure 7 (1) MIN MAX UNIT tsu(D-H1L)R Setup time, data before H1 low (read) 5(2) ns th(H1L-D)R Hold time, data after H1 low (read) –1(2) tsu(RDY-H1H) Setup time, RDY before H1 high 5 th(H1H-RDY) Hold time, RDY after H1 high –1(2) td(A-RDY) Delay time, address valid to RDY P – 6(2)(3) tv(A-D) Valid time, data valid after address 0 wait state, CL = 30 pF 6(2) PAGEx, or STRB valid 1 wait state tc(H) + 6(2) (1) These timings assume a similar loading of 30 pF on all pins. (2) Not production tested (3) P = tc(H) / 2 (when duty cycle equals 50%). 6.8 Timing Requirements for XF0 and XF1 when Executing LDFI or LDII see Figure 8 MIN MAX UNIT tsu(XF1-H1L) Setup time, XF1 before H1 low 4(1) ns th(H1L-XF1) Hold time, XF1 after H1 low 0(1) (1) Not production tested 10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated Product Folder Links: SM320VC33 SMJ320VC33 |
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