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ADC10030 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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ADC10030 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 17 page Timing Diagram (Continued) Functional Description The ADC10030 maintains excellent dynamic performance for input signals up to and exceeding half the clock fre- quency. The use of an internal sample-and-hold amplifier (SHA) enables sustained dynamic performance for signals of input frequency beyond the clock rate, lowers the converter’s input capacitance and reduces the number of external com- ponents required. The analog signal at V IN that is within the voltage range set by V REF+ S and VREF− S are digitized to ten bits at up to 30 MSPS. Input voltages below V REF− S will cause the out- put word to consist of all zeroes. Input voltages above V REF+ S will cause the output word to consist of all ones. V REF+ S has a range of 2.6V to 3.8V, while VREF− S has a range of 1.7V to 2.8V. V REF+ S should always be at least 1.0V more positive than V REF−S. Data is acquired at the falling edge of the clock and the digi- tal equivalent of that data is available at the digital outputs 2.0 clock cycles plus t OD later. The ADC10030 will convert as long as the clock signal is present at pin 9 and the PD pin is low. The Output Enable pin (OE), when low, enables the out- put pins. The digital outputs are in the high impedance state when the OE pin or the PD pin is high. Applications Information 1.0 THE ANALOG INPUT The analog input of the ADC10030 is a switch (transmission gate) followed by a switched capacitor amplifier. The capaci- tance seen at the input changes with the clock level, appear- ing as about 3 pF when the clock is low, and about 5 pF when the clock is high. This small change in capacitance can be reasonably assumed to be a fixed capacitance. Care should be taken to avoid driving the input beyond the supply rails, even momentarily, as during power-up. The CLC409 has been found to be a good device to drive the ADC10030 because of its wide bandwidth, low distortion and minimal Differential Gain and Differential Phase. The CLC409 performs best with a feedback resistor of about 100 Ω. Care should be taken to keep digital noise out of the analog input circuitry to maintain highest noise performance. 2.0 REFERENCE INPUTS Note: Throughout this data sheet reference is made to VREF+ and to VREF−. These refer to the internal voltage across the reference ladder and are, nominally, VREF+ S and VREF− S, respectively. Figure 4 shows a simple reference biasing scheme with minimal components. While this circuit might suffice for some applications, it does suffer from thermal drift because the external will have a different temperature coefficient than the on-chip resistors. Also, the on-chip resistors, while well matched to each other, will have a large tolerance compared with any external resistors, causing the value of V REF+ and V REF− to be somewhat variable. The V REF+ F and VREF− F pins should each be bypassed to AGND with 10 µF tantalum or electrolytic capacitors and 0.1 µF ceramic capacitors. The circuit of Figure 5 is an improvement over the circuit of Figure 4 in that the positive end of the reference ladder is de- fined with a reference voltage. This reduces problems of high reference variability and thermal drift. In addition to the usual V REF+F and VREF−F reference in- puts, the ADC10030 has two sense outputs for precision control of the ladder voltages. These sense outputs (V REF+ S and V REF− S) compensate for errors due to IR drops be- tween the source of the reference voltages and the ends of the reference ladder itself. With the addition of two op-amps, the voltages at the top and bottom of the reference ladder can be forced to the exact value desired, as shown in Figure 6. DS101064-17 FIGURE 2. AC Test Circuit DS101064-16 FIGURE 3. t EN,tDIS Test Circuit www.national.com 11 |
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