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LM3632AYFFR Datasheet(PDF) 8 Page - Texas Instruments |
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LM3632AYFFR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 64 page LM3632A SNVSA63A – APRIL 2015 – REVISED SEPTEMBER 2015 www.ti.com 6.6 I 2C Timing Requirements (SDA, SCL) (1) Over operating free-air temperature range (unless otherwise noted)(see Figure 1). MIN NOM MAX UNIT ƒSCL Clock frequency 400 kHz 1 Hold time (repeated) START condition 0.6 µs 2 Clock low time 1.3 µs 3 Clock high time 600 ns 4 Set-up time for a repeated START condition 600 ns 5 Data hold time 50 ns 6 Data set-up time 100 ns 7 Rise time of SDA and SCL 20 + 0.1Cb 300 ns 8 Fall time of SDA and SCL 15 + 0.1Cb 300 ns 9 Set-Up time between a STOP and a START condition 1.3 µs Cb Capacitive load for each bus line 10 200 pF (1) Limits set by characterization and/or simulation only. Figure 1. I2C Timing Parameters 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM3632A |
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