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TPS65010RGZT Datasheet(PDF) 44 Page - Texas Instruments

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Part # TPS65010RGZT
Description  Power and Battery Management IC for Li-Ion Powered Systems
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65010RGZT Datasheet(HTML) 44 Page - Texas Instruments

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TPS65010
SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015
www.ti.com
Table 23. CORE Settings (continued)
CORE2
CORE1
CORE0
VCORE
1
1
1
1.6 V
Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low-
powermode. In low-powermode, CORE2 is effectively '0', and CORE1, CORE0 take on the values programmed
at CORELP1 and CORELP0, default '10' giving VCORE = 1.1V as default in low-powermode. When low-
powermode is exited, VCORE reverts to the value set by CORE2, CORE1 and CORE0.
Bit 1 - VIB:
0 = disables the VIB output transistor.
1 = enables the VIB output transistor to drive the vibrator motor.
Bit 0 - CORE DISCHARGE:
0 = disables the active discharge of the VCORE converter output.
1 = enables the active discharge of the VCORE converter, output, when the converter is disabled.
7.6.14 VREGS1Register (Address: 0Eh—Reset: 88h)
VREGS1Register
VREGS1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LDO2 enable
LDO2 OFF /
LDO21
LDO20
LDO1 enable
LDO1 OFF /
LDO11
LDO10
nSLP
nSLP
Default
1
0
0
0
1
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low-
powermode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or
simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.
Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF / nSLP bits is shown in Table 24. See the power-on
sequencing section for details of low-power mode.
Table 24. LDO2 Enable and LDO2 OFF/nSLP Functions
LDO2 ENABLE
LDO2 OFF / nSLP
LDO STATUS IN NORMAL MODE
LDO STATUS IN LOW-POWER MODE
0
X
OFF
OFF
1
0
ON, full power
ON, reduced power and performance
1
1
ON, full power
OFF
Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If so desired, this can be changed at the
same time as it is enabled through the serial interface.
Table 25. LDO2 Settings
LDO21
LDO20
VLDO2
0
0
1.8 V
0
1
2.5 V
1
0
2.75 V
1
1
3.0 V
Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF / nSLP bits is shown in the following table. See the
power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage
may force a system power on reset if the increase is in the 10% or greater range.
Table 26. LDO1 Enable and LDO1 OFF/nSLP Functions
LDO1 ENABLE
LDO1 OFF / nSLP
LDO STATUS IN NORMAL MODE
LDO STATUS IN LOW-POWER MODE
0
X
OFF
OFF
44
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