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TLC59116FIPWR Datasheet(PDF) 8 Page - Texas Instruments |
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TLC59116FIPWR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 38 page RL RT CL VO VCC VI Open VCC GND PULSE GENERATOR DUT SCL SDA Protocol START (S) Condition Bit 7 MSB (A7) Bit 6 (A6) Bit 7 (D1) Bit 8 (D0) Acknowledge (A) STOP Condition (P) tBUF tLOW 1/fSCL tHD;STA TSU;STO tSU;DAT tSU;STA tHD;DAT tVD;DAT tVD;ACK tHIGH tf tr t BUF t LOW t HD;STA t HD;STA t SP t SU;STO t SU;STA t SU;DAT t HD;DAT t HIGH t f SCL P Sr S P SDA t r TLC59116F SCLS714C – MARCH 2009 – REVISED SEPTEMBER 2015 www.ti.com Parameter Measurement Information (continued) Figure 4. Definition of Timing A. Rise and fall times refer to VIL and VIH. Figure 5. I2C Bus Timing A. Load resistor, RL, for SDA and SCL > 1 kΩ (3 mA or less current) B. Load capacitance, CL, includes jig and probe capacitance C. Termination resistance, RT, should be equal to the output impedance ZO of the pulse generators. Figure 6. Test Circuit for Switching Characteristics 8 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TLC59116F |
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