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2015-11-0004

PT0225-6

11/25/15

10

PT7C4302

Real-time Clock Module (3-wire Interface)

a)

Trickle Charger Select

Control the selection of the trickle charger.

TCS

Data

Description

Read/

Write

Other patent

Disable the trickle charger

* Default 0101

1010

Enable the trickle charger

b)

Diode Select

Select whether one diode or two diodes are connected between VCC2 and VCC1.

DS

Data

Description

Read/

Write

00 or 11

The trickle charger is disabled independently of TCS.

* Default

01

One diode is selected.

10

Two diodes are selected.

c)

Resistor Select

Select whether one diode or two diodes are connected between VCC2 and VCC1.

RS

Data

Description

Read/

Write

00

No resistor.

* Default

01

R1 with typ. 2k

10

R2 with typ. 4k

11

R3 with typ. 8k

Communication

1.

3-wire Interface

a)

Command Byte

Figure 1 Command byte

The command byte is shown in Figure 1. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If

it is 0, writes to the PT7C4302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1

through 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or

read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).

b)

RST and SCL Signal

All data transfers are initiated by driving the RST input high and terminated by driving the RST input low. A clock cycle is a

sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and

data bits are output on the falling edge of clock. If the RST input is low all data transfer terminates and the SDA pin goes to a high

impedance state. Data transfer is illustrated in Figure 2 and Figure 3. At power-up, RST must be a logic 0 until VCC > 2.0V. Also

SCLK must be at a logic 0 when RST is driven to a logic 1 state.