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PI6CDBL401BZHIEX Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6CDBL401BZHIEX Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
1 / 16 page 1 www.pericom.com PI6CDBL401B Rev.C 03/23/16 All trademarks are property of their respective owners. PI6CDBL401B Block Diagram Description The PI6CDBL401B is a 4-output low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with integrated output terminations providing Zo=100Ω. The device has 4 output en- ables for clock management, and 3 selectable SMBus addresses. Features Î Î 4x 100MHz low power HCSL or LVDS compatible outputs Î Î PCIe 3.0, 2.0 and 1.0 compliant Î Î Programmable output amplitude and slew rate Î Î Core supply voltage of 3.3V +/-10% Î Î Output supply voltage of 1.8V, 2.5V and 3.3V Î Î Industrial ambient operation temperature Î Î Available in lead-free package: 32-TQFN 4-Output Low Power PCIE GEN1-2-3 Buffer CONTROL LOGIC ZDB PLL OE(3:0)# CLK_IN CLK_IN# SADR_tri HIBW_BYPM_LOBW# CKPWRGD_PD# SDATA_3.3 SCLK_3.3 CLK(3:0) 4 Applications Î Î PCIe 3.0/2.0/1.0 clock distribution 16-0064 |
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