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PI6CDBL401BZHIEX Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI6CDBL401BZHIEX Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
8 / 16 page 8 www.pericom.com PI6CDBL401B Rev.C 03/23/16 All trademarks are property of their respective owners. PI6CDBL401B 4-Output Low Power PCIE GEN1-2-3 Buffer Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics (T A = -40~85 o C; VDD = 3.3V+/-10%; VDDO = 3.3V+/-10%; VDDO = 2.5V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol Parameters Condition Min. Type Max. Units t DC Duty Cycle1 Measured differentially, PLL Mode 45 55 % t DCD Duty Cycle Distortion1,3 Measured differentially, Bypass Mode@100MHz -1 0 1 % t pdBYP Skew, Input to Output1,4 Bypass Mode, VT = 50% 2500 4500 ps t pdPLL PLL Mode VT = 50% -250 250 ps t skew Skew, Output to Output1,2 VT = 50% 25 50 ps t jcyc-cyc Jitter, Cycle to cycle1,2 PLL mode @100MHz output 50 ps Additive Jitter in Bypass Mode @100MHz output 0.1 25 ps Note: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Measured from differential waveform 3. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4. All outputs at default slew rate 5. The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN. Electrical Characteristics–Current Consumption (T A = -40~85 o C; See Test Loads for Loading Conditions) Symbol Parameters Condition Min. Type Max. Units I DDAOP Operating Supply Current1 VDDA+VDDR, PLL Mode, @100MHz, typical value under VDDO = 1.8V 37 45 mA I DDOP VDD1.8, All outputs active @100MHz, typical value under VDDO = 1.8V 52 60 mA I DDAPD Powerdown Current1,2 VDDA+VDDR, PLL Mode, @100MHz 1 mA I DDPD VDD1.8, Outputs Low 1.8 mA Note: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Input clock stopped. 16-0064 |
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