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PI6C5946002ZHIE Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C5946002ZHIE Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
1 / 12 page 1 PI6C5946002 Rev A 11/04/14 Block Diagram Features Î Î Input Clock Frequency up to 6 GHz Typical Î Î Maximum Input Data Rate up to 12 Gbps Typical Î Î 2 pairs of differential CML outputs Î Î Low additive jitter, < 0.05ps (max) Î Î Input accepts: CML, LVDS, CML, SSTL input level Î Î Output to Output skew: <20ps Î Î Operating Temperature: -40oC to 85oC Î Î Power supply: 3.3V ±10% or 2.5V ±5% Î Î Packaging (Pb-free & Green) Î Î 16-pin TQFN available Description The PI6C5946002 is a high-performance low-skew 1-to-2 CML clock or data fanout buffer. The inputs accept CML, LVDS, CML and SSTL signals with internal termination resistors. PI6C5946002 is ideal for clock / data distribution applications. Pin Configuration REF_IN+ VTH REF_IN- Q0+ Q0- Q1+ Q1- D LE Q EN Q0+ Q0- Q1+ Q1- 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 REF_IN+ VTH VREF-AC REF_IN- 6 GHz / 12 Gbps Clock / Data Fanout Buffer with Internal Termination PI6C5946002 14-0180 |
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