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UCC28722DBVT Datasheet(PDF) 5 Page - Texas Instruments |
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UCC28722DBVT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 34 page  UCC28722 www.ti.com SLUSBL7B – DECEMBER 2013 – REVISED OCTOBER 2015 6.5 Electrical Characteristics over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS SUPPLY INPUT IRUN Supply current, run IDRV = 0, run state 2.00 2.65 mA IWAIT Supply current, wait IDRV = 0, wait state 95 170 µA ISTART Supply current, start IDRV = 0, VVDD = 18 V, start state, IHV = 0 1.0 1.5 µA IFAULT Supply current, fault IDRV = 0, fault state 2.00 2.65 mA UNDERVOLTAGE LOCKOUT VVDD(on) VDD turnon threshold VVDD low to high 19 21 23 V VVDD(off) VDD turnoff threshold VVDD high to low 7.2 7.7 8.3 V VS INPUT VVSR Regulating level Measured at no-load condition, TJ = 25°C (1) 3.99 4.05 4.11 V VVSNC Negative clamp level IVS = –300 µA, volts below ground 190 250 325 mV IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA CS INPUT VCST(max) Max CS threshold voltage VVS = 3.7 V 730 780 820 mV VCST(min) Min CS threshold voltage VVS = 4.35 V 170 190 220 mV KAM AM control ratio VCST(max) / VCST(min) 3.6 4.0 4.4 V/V VCCR Constant current regulating level CC regulation constant 314 330 347 mV KLC Line compensation current ratio IVSLS = –300 µA, IVSLS / current out of CS pin 24.0 25.0 28.6 A/A TCSLEB Leading-edge blanking time DRV output duration, V CS = 1 V 230 290 355 ns DRIVER IDRS(max) Maximum DRV source current VDRV = 2 V, VVDD = 9 V, VVS = 3.85 V 31 37 42 mA IDRS(min) Minimum DRV source current VDRV = 2 V, VVDD = 9 V, VVS = 4.30 V 15 19 23 mA RDRVLS DRV low-side drive resistance IDRV = 10 mA 1 2.4 Ω VDRCL DRV clamp voltage VVDD = 35 V 5.9 7 V RDRVSS DRV pulldown in start state 20 25 k Ω TIMING fSW(max) Maximum switching frequency VVS = 3.7 V 72 80 89 kHz fSW(min) Minimum switching frequency VVS = 4.35 V 570 650 750 Hz tZTO Zero-crossing timeout delay 2.4 3.1 3.7 µs PROTECTION VOVP Overvoltage threshold At VS input, TJ = 25°C (1) 4.49 4.60 4.75 V VOCP Overcurrent threshold At CS input 1.4 1.5 1.6 V IVSL(run) VS line-sense run current Current out of VS pin increasing 188 225 277 µA IVSL(stop) VS line-sense stop current Current out of VS pin decreasing 70 80 100 µA KVSL VS line sense ratio IVSL(run) / IVSL(stop) 2.45 2.80 3.05 A/A TJ(stop) Thermal shutdown temperature Internal junction temperature 165 °C CABLE COMPENSATION Cable compensation maximum VCBC(max) Voltage at CBC at full load 2.9 3.1 3.5 V voltage VCBC = open, change in VS regulating level at full VCVS(min) Minimum compensation at VS –55 –15 25 mV load VCBC = 0 V, change in VS regulating level at full VCVS(max) Maximum compensation at VS 270 320 385 mV load (1) The regulating level and over voltage at VS decreases with temperature by 0.8 mV/ ˚C. This compensation is included to reduce the power supply output voltage variance over temperature. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: UCC28722 |
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