TPS24710, TPS24711

TPS24712, TPS24713

SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015

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8.3 Feature Description

8.3.1 DETAILED PIN DESCRIPTIONS

8.3.1.1 EN

Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor

divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the

TPS24710/11/12/13 that has latched off due to a fault condition. This pin should not be left floating.

8.3.1.2 FLT

FLT is assigned for TPS24712/13. This active-high open-drain output assumes high-impedance when

TPS24712/13 has remained in current limit long enough for the fault timer to expire. The behavior of the FLT pin

depends on the version of the IC. The TPS24712 operates in latch mode and the TPS24713 operates in retry

mode. In latch mode, a fault timeout disables the external MOSFET and holds FLT in open drain condition. The

latched mode of operation is reset by cycling EN or VCC. In retry mode, a fault timeout first disables the external

MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This

process repeats as long as the fault persists. In retry mode, the FLT pin goes open-drain whenever the external

MOSFET is disabled by the fault timer. In a sustained fault, the FLT waveform becomes a train of pulses. The

FLT pin does not assert if the external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This

pin can be left floating when not used.

8.3.1.3 FLTb

FLTb is assigned for TPS24710/11. This active-low open-drain output pulls low when TPS24710/11/12/13 has

remained in current limit long enough for the fault timer to expire. The behavior of the FLTb pin depends on the

version of the IC. The TPS24710 operates in latch mode and the TPS24711 operates in retry mode. In latch

mode, a fault timeout disables the external MOSFET and holds FLTb low. The latched mode of operation is reset

by cycling EN or VCC. In retry mode, a fault timeout first disables the external MOSFET, next waits sixteen

cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as the

fault persists. In retry mode, the FLTb pin is pulled low whenever the external MOSFET is disabled by the fault

timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if the

external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This pin can be left floating when not

used.

8.3.1.4 GATE

This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external

TPS24710/11/12/13 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold

compared with the current-limit threshold derived from the MOSFET power-limit scheme (see PROG). If the

disabled by the following three conditions:

1. GATE is pulled down by an 11-mA current source when

–

–

–

2. GATE is pulled down by a 1 A current source for 13.5 µs when a hard output short circuit occurs and

complete, an 11-mA sustaining current ensures that the external MOSFET remains off.

3. GATE is discharged by a 20 k

Ω resistor to GND if the chip die temperature exceeds the OTSD rising

threshold.

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