6

PS-01

04/19/11

PI6C49004A

PCIe®Gen 2 Networking Clock Generator

Byte 1: Control Register

Bit

Description

Type

Power Up Con-

dition

Output(s) Affected

Notes

7

OE for 32.256M_Out1

RW

1

32.256M_Out1

0 = disabled

1 = enabled

6

OE for 50M_Out1

RW

1

50M_Out1

0 = disabled

1 = enabled

5

OE for 33/66/133M_Out1

RW

1

33/66/133M_Out1

0 = disabled

1 = enabled

4

OE for 100M_Q11 HCSL output

RW

1

100M_Q11

0 = disabled

1 = enabled

3

OE for 100M_Q10 HCSL output

RW

0

100M_Q10

0 = disabled

1 = enabled

2

OE for 100M_Q09 HCSL output

RW

0

100M_Q9

0 = disabled

1 = enabled

1

OE for 100M_Q08 HCSL output

RW

0

100M_Q8

0 = disabled

1 = enabled

0

OE for 100M_Q07 HCSL output

RW

0

100M_Q7

0 = disabled

1 = enabled

Byte 2: Control Register

Bit

Description

Type

Power Up Con-

dition

Output(s) Affected

Notes

7

Frequency margining select bit FS6 RW

1

33/66/133M_Out1

See 33/66/133MHz

Frequency Margin-

ing Table on Page 3

6

Frequency margining select bit FS5 RW

0

5

Frequency margining select bit FS4 RW

0

4 to 0

Reserved

R

Undefined

Not Applicable

Byte 0 - Bit 6 and Bit 5 Functionality

Bit 6

Bit 5

Description

0

X

(PD_RESET = "H" will enable all outputs; SMBus cannot control each output.)

1

0

Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE

1

1

Enable outputs according to the SMBus default values; SMBus can control each output.

PD_RESET HW pin/signal = DON'T CARE

11-0104