5

PS9023A

11/20/09

PI6C49003

Networking Clock Generator

Byte 1: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7

OE for 32.256M_Out1

RW

1

32.256M_Out1

0 = disabled

1 = enabled

6

OE for 50M_Out1

RW

1

50M_Out1

0 = disabled

1 = enabled

5

OE for 33/66/133M_Out1

RW

1

33/66/133M_Out1

0 = disabled

1 = enabled

4

Reserved

RW

1

Not Applicable

3 to 0

Reserved

RW

0

Not Applicable

Byte 2: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7

Frequency margining select bit FS6

RW

1

33/66/133M_Out1

See 33/66/100MHz

Frequency Select

Table on Page 3

6

Frequency margining select bit FS5

RW

0

5

Frequency margining select bit FS4

RW

0

4 to 0

Reserved

R

Undefined

Not Applicable

Byte 3: Control Register

Bit

Description

Type

Power Up Con-

dition

Output(s) Affected

Notes

7

OE for 100M_Q4 HCSL Output

RW

0

100M_Q4

0 = disabled

1 = enabled

5

OE for 100M_Q3 HCSL Output

RW

0

100M_Q3

0 = disabled

1 = enabled

4

OE for 100M_Q2 HCSL Output

RW

0

100M_Q2

0 = disabled

1 = enabled

2

OE for 100M_Q1 HCSL Output

RW

1

100M_Q1

0 = disabled

1 = enabled

1

OE for 100M_Q0 HCSL Output

RW

1

100M_Q0

0 = disabled

1 = enabled

3, 6

Reserved

RW

0

Not Applicable

0

Reserved

R

Undefined

Not Applicable

Byte 0 - Bit 6 and Bit 5 Functionality

Bit 6

Bit 5

Description

0X

PD_RESET HW pin/signal = enabled

10

Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE

11

Enable all outputs, PD_RESET HW pin/signal = DON'T CARE

09-0097