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PI6C49S1504 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C49S1504 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
1 / 10 page PI6C20800B PI6C49S1504 Block Diagram Features Î Î 4 differential outputs with 2 banks Î Î User configurable output signaling standard for each bank: LVDS or LVPECL or HCSL Î Î LVCMOS reference output up to 200MHz Î Î Up to 1.5GHz output frequency for differential outputs Î Î Ultra low additive phase jitter: < 0.03 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) Î Î Selectable reference inputs support either single-ended or differential or Xtal Î Î Low skew between outputs within banks (<40ps) Î Î Low delay from input to output (Tpd typ. < 1.5ns) Î Î Separate Input output supply voltage for level shifting Î Î 2.5V / 3.3V power supply Î Î Industrial temperature support Î Î TSSOP-28 package 1 PI6C49S1504 RevA 04/01/13 Pin Configuration (28-Pin TSSOP) Description The PI6C49S1504 is a high performance fanout buffer device- which supports up to 1.5GHz frequency. The device also uses Pericom's proprietary input detection technique to make sure illegal input conditions will be detected and reflected by output states. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. Applications Î Î Networking systems including switches and Routers Î Î High frequency backplane based computing and telecom platforms High Performance Selectable 1:4 Differential Fanout Buffer 1 2 3 CLK_SEL1 4 CLK0 5 CLK_SEL0 6 CLK1 7 QB0 8 nCLK0 QA0 VDDO OpModeA0 QA1 nQA1 nCLK1 28 27 26 25 24 23 22 21 VEE/GND NC OpModeA1 nQA0 nQB0 9 Xtal_In 20 OpModeB1 10 Xtal_Out 19 OpModeB0 11 IREF 18 VDDO 12 VDD 17 QB1 13 16 Ref_out 14 15 Sync_OE nQB1 OSC 2 QA[0:1] QB[0:1] Ref_Out OPMODEA[1:0] OPMODEB[1:0] CLK_SEL[1:0] Sync_OE Iref nCLK1 CLK1 CLK0 X1 X2 nCLK0 2 Sync 13-0025 |
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