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LS7082N Datasheet(PDF) 1 Page - LSI Computer Systems |
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LS7082N Datasheet(HTML) 1 Page - LSI Computer Systems |
1 / 4 page QUADRATURE CLOCK CONVERTER FEATURES: • x1, x2 and x4 mode selection • Up to 16MHz output clock frequency • INDEX input and output • UP/DOWN indicator output • Programmable output clock pulse width • On-chip filtering of inputs for optical or magnetic encoder applications. • TTL and CMOS compatible I/Os • +4.5V to +10V operation (VDD - VSS) • LS7082N (DIP); LS7082N-S (SOIC ) - See Figure 1 INPUT/OUTPUT DESCRIPTION: VDD (Pin 1) Supply Voltage positive terminal. INDX (Pin 2) Encoder Index pulses are applied to this input. RBIAS (Pin 3) Input for external component connection. A resistor con- nected between this input and VSS adjusts the output clock pulse width (Tow). For proper operation, the output clock pulse width must be less than or equal to the A, B pulse separation (TOW ≤ TPS). VSS (Pin 4) Supply Voltage negative terminal. A (Pin 5) Quadrature Clock Input A. This input has a filter circuit to validate input logic level and eliminate encoder dither. x2 (Pin 8) A low level applied to this input selects x2 mode of opera- tion. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. B (Pin 9) Quadrature Clock Input B. This input has a filter circuit identical to input A. x4/x1 (Pin 10) This input selects between x1 and x4 modes of operation. See Table 1 for Mode Selection Truth Table and Figure 2 for Input/Output timing relationship. UP/DN (Pin 11) The count direction at any instant is indicated at this output. An UP count direction is indicated by a high, and a DOWN count direction is indicated by a low (See Figure 2). DNCK (Pin 12) This DOWN Clock output consists of low-going pulses gen- erated when A input lags the B input (See Figure 2). UPCK (Pin 13) This UP Clock output consists of low-going pulses gener- ated when A input leads the B input (See Figure 2). INDX (Pin 14) This output consists of low-going pulses generated by a positive clock transition at the A input when INDX input is high and B input is low and a negative clock transition at the B input when INDX input is high and A input is high. (See Figure 2). NOTE: All unused input pins must be tied to VDD or VSS. DESCRIPTION: The LS7082N is a CMOS quadrature clock converter. Quad- rature clocks derived from optical or magnetic encoders, when applied to the A and B Inputs of the LS7082, are converted to strings of Up Clocks and Down Clocks. Pulses derived from the Index Track of an encoder, when applied to the INDX input, produce absolute position reference pulses which are syn- chronized to the Up Clocks and Down Clocks. These outputs can be interfaced directly with standard Up/Down counters for direction and position sensing of the encoder. April 2006 7082N-041906-1 TABLE 1. MODE SELECTION TRUTH TABLE x2 Input x4/x1 Input MODE 0 Don’t Care x2 1 0 x1 1 1 x4 LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 LS7082N UL ® A3800 1 2 3 4 5 6 7 UPCK DNCK UP/DN x4/x1 B x2 V DD (+V) INDX RBIAS V SS (-V) A NC NC 14 13 12 11 8 9 10 FIGURE 1 PIN ASSIGNMENT - TOP VIEW INDX |
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