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TPS3702CX33QDDCRQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS3702CX33QDDCRQ1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page 1 2 3 6 5 4 VDD SET GND SENSE UV OV TPS3702-Q1 www.ti.com SBVS261B – APRIL 2015 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DDC Package SOT-6 Top View Pin Functions PIN I/O DESCRIPTION NO. NAME Active-low, open-drain undervoltage output. This pin goes low when the SENSE voltage falls 1 UV O below the internally set undervoltage threshold (VIT–). See the timing diagram in Figure 1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage. 2 GND — Ground Input for the monitored supply voltage rail. When the SENSE voltage goes below the 3 SENSE I undervoltage threshold, the UV pin is driven low. When the SENSE voltage goes above the overvoltage threshold, the OV pin is driven low. Use this pin to configure the threshold voltages. 4 SET I Refer to Table 3 for the desired configuration. Supply voltage input pin. To power the device, connect a voltage supply (within the range of 2 V 5 VDD I and 18 V) to VDD. Good analog design practice is to place a 0.1- μF ceramic capacitor close to this pin. Active-low, open-drain overvoltage output. This pin goes low when the SENSE voltage rises 6 OV O above the internally set overvoltage threshold (VIT+). See the timing diagram in Figure 1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS3702-Q1 |
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