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LP5952 Datasheet(PDF) 3 Page - Texas Instruments |
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LP5952 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 29 page OFF GATE OUT IN 1 2 3 6 5 4 VS GND LM5050-1, LM5050-1-Q1 www.ti.com SNVS629E – MAY 2011 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DDC Package 6-Pin SOT Top View Pin Functions PIN I/O DESCRIPTION NO. NAME The main supply pin for all internal biasing and an auxiliary supply for the internal gate drive 1 VS I charge pump. Typically connected to either VOUT or VIN; a separate supply can also be used. 2 GND PWR Ground return for the controller A logic high state at the OFF pin will pull the GATE pin low and turn off the external MOSFET. 3 OFF I Note that when the MOSFET is off, current will still conduct through the FET's body diode. This pin should may be left open or connected to GND if unused. 4 IN I Voltage sense connection to the external MOSFET Source pin. Connect to the Gate of the external MOSFET. Controls the MOSFET to emulate a low forward- 5 GATE O voltage diode. 6 OUT O Voltage sense connection to the external MOSFET Drain pin. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5050-1 LM5050-1-Q1 |
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