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SP7652EB Datasheet(PDF) 10 Page - Sipex Corporation |
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SP7652EB Datasheet(HTML) 10 Page - Sipex Corporation |
10 / 15 page 10 f. Select the ratio of Rz / R1 gain for the desired gain bandwidth Rz = R1 (Vramp_pp / Vin_max) (fco) [fz_ESR / (fp_LC) ^ 2] g. Calculate Cz by placing the zero at 1/10 of the output filter pole frequency Cz = 1 / 0.1(2 π) (Rz) (fp_LC) h. Calculate Cp by placing the second pole at ½ of the switching frequency Cp = 1 / π (Rz) (fs) As a particular example, consider for the following SP7652EB with a Type II Voltage Loop Compensation component selections: Vin = 5 to 15V Vout = 3.30V @ 0 to 8A load Select L = 1.5uH => yield ≈ 35% of maximum 8A output current ripple. Select Cout = 330uF Tantalum capacitor (Resr ≈ 10mΩ) fs = 600khz SP7652 internal Oscillator Frequency Vramp_pp = 1.0V SP7652 internal Ramp Peak to Peak Amplitude Step by step design procedures: a. fco = 600khz / 10 = 60khz b. fp_LC = 1 / 2 π [(1.5uH) (330uF)] ^ 1/2 ≈ 7khz c. fz_ESR = 1 / 2 π (10mΩ) (330uF) ≈ 50khz d. R1 = 68.1k Ω, 1% e. R2 = 68.1k Ω / [(3.30V / 0.80V) – 1] ≅ 21.5kΩ, 1% f. Rz = 68.1k Ω (1.0V / 15V) (60khz) [50khz / (7khz) ^ 2] ≈ 280kΩ, 1% g. Cz = 1 / 0.1 (2 π) (280kΩ) (7khz) ≈ 820pF, COG h. Cp = 1 / π (280kΩ) (600khz) ≈ 2.2pF l. Cf1 = 100pF to stabilize SP7652EU internal Error Amplify +5V OUTPUT WITH A TYPE II COMPENSATION APPLICATION SCHEMATIC SP7652EU with Tantalum output capacitor configures for Vin = 12V, Vout = +5V at 0-8A output current. Figure 16 and 17 show output voltage ripple less than 53mV at no load to 8A load. Figure 18 and 19 show typical 92% efficiency and 0.3% load regulation plots with a Type II compensation application circuits. |
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