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UC3846N Datasheet(PDF) 16 Page - Texas Instruments |
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UC3846N Datasheet(HTML) 16 Page - Texas Instruments |
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1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vin C/S SS VREF C/S- C/S+ E/A+ E/A- COMP CT SHUTDOWN VIN BOUT VC GND AOUT SYNC RT UC1846, UC1847, UC2846 UC2847, UC3846, UC3847 SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines • Place a low ESR and ESL decoupling capacitor CREF in the 1-µF to 2.2-µF range, preferably ceramic, from VREF pin to GND. • The EA+ is a non-inverting input, the EA– is an inverting input and the COMP is the output of the error amplifier. Place resistor and capacitor series network between EA+ pin and COMP pin, and reduce the trace of resistor and capacitor series network as much as possible. • Place a low ESR and ESL capacitor CT, preferably ceramic, from CT pin to GND, and place CT close to UCx846/7 as much as possible. • Place a resistor RT from RT pin to GND, and place RT close to UCx846/7 as much as possible. 10.2 Layout Example Figure 12. UCx84x Layout Example 16 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated Product Folder Links: UC1846 UC1847 UC2846 UC2847 UC3846 UC3847 |
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