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TPS65020RHAR Datasheet(PDF) 27 Page - Texas Instruments

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Part # TPS65020RHAR
Description  Power Management IC
Download  53 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65020RHAR Datasheet(HTML) 27 Page - Texas Instruments

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8.5 Programming
8.5.1 System Reset + Control Signals
The RESPWRON signal can be used as a global reset for the application. It is an open-drain output. The
RESPWRON signal is generated according to the power-good comparator of VRTC, and remains low for tnrespwron
seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an
external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the
HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
The VDCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when
HOT_RESET is asserted. Other I2C registers are not affected. Generally, the VDCDC3 converter is set to its
default voltage with one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage,
undervoltage lockout (UVLO) condition, RESPWRON active, both VDCDC3-converter AND VDCDC1-converter
disabled. In addition, the voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx
is the state before VDCDC1 was disabled. PB_IN and PB_OUT
In the TPS65020 the PB_IN pin is defined as an input. It is active high and debounces the input signal. For
example from a push button, before passing it to a latch associated with PB_OUT (active-low). This feature
allows the implementation of a push-button on-off-switch. PB_OUT is actively pulled low per default. See the
Application Information section. Interrupt Management and the INT Pin
The INT pin combines the outputs of the PGOOD comparators from each DC-DC converter and LDOs. The INT
pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register
is read through the serial interface, any active bits are then blocked from the INT output pin.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO interrupts
because this provides the POWER_OK function.
8.5.2 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65020 has a 7-bit address: 1001000,
other addresses are available upon contact with the factory. Attempting to read data from the register addresses
not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65020 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65020 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65020 device must leave the data line high to enable the master to generate the stop
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