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TPS65020 Datasheet(PDF) 41 Page - Texas Instruments

Part # TPS65020
Description  Power Management IC
Download  53 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS65020 Datasheet(HTML) 41 Page - Texas Instruments

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t
=2
(reset)
x128x
(1V-0.25V)xC(reset)
2 A
m
()
VOUT
DEFDCDCx
=V
x
R1+R2
R2
R1=R2x
VOUT
VDEFDCDCx
-R2
()
VDCDC3
DCDC3_EN
DEFDCDC3
AGND
PGND
L3
R1
R2
VO
L
CO
VCC
VINDCDC3
CI
1 F
m
10R
V(bat)
TPS65020
www.ti.com
SLVS607D – SEPTEMBER 2005 – REVISED JANUARY 2016
Figure 38 illustrations how to use an external resistor divider at DEFDCDCx.
Figure 38. External Resistor Divider
When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input
voltage V(bat). The total resistance (R1+R2) of the voltage divider must be kept in the 1-MR range to maintain a
high efficiency at light load.
V(DEFDCDCx) = 0.6 V
(12)
9.2.2.5 VRTC Output
The VRTC output is typically connected to the VCC_Batt pin of a Intel PXA270 processor. During power-up of the
processor, the TPS65020 internally switches from the LDO or the backup battery to the system voltage
connected at the VSYSIN pin (see Figure 30). It is required to add a capacitor of 4.7-
μF minimum to the VRTC
pin, even the output may be unused.
9.2.2.6 LDO1 and LDO2
The LDOs default voltage is 1.1 V for LDO2 and 1.3 V for LDO1. They are intended to provide power to
VCC_PLL and the VCC_SRAM pin on a PXA270 processor. The minimum output capacitor required is 2.2
μF.
The LDOs output voltage is changed to different voltages between 1 V and 3.3 V using the I2C interface.
Therefore, they can also be used as general-purpose LDOs in applications powering processors different from
PXA270. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to
connect the lowest voltage available in the system, and providing the highest efficiency.
9.2.2.7 TRESPWRON
This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.
The timing is generated by charging and discharging the capacitor with a current of 2
μA between a threshold of
0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.
While there is no real upper and lower limit for the capacitor connected to TRESPWRON, TI recommends not
leaving signal pins open.
where
t(reset) is the reset delay time
C(reset) is the capacitor connected to the TRESPWRON pin
(13)
Copyright © 2005–2016, Texas Instruments Incorporated
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