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SP5301 Datasheet(PDF) 6 Page - Sipex Corporation |
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SP5301 Datasheet(HTML) 6 Page - Sipex Corporation |
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6 / 13 page  6 SP5301DS/10 SP5301 Universal Serial Bus Transceiver © Copyright 2000 Sipex Corporation The SP5301 incorporates a receive error circuit. This error circuit outputs CMOS signals on the receive error pin (RERR) and the receive single ended zero pin (RSE0) under specific conditions from the USB bus. When OE is asserted LOW, it enables the USB driver to transmit data on the D+ and D- output pins. The receive error circuit is disabled in this condition and both RERR and RSE0 are forced low. The receive error circuit is activated in receive mode when OE is HIGH. The receive error circuit will signal an error state when both D+ and D- are HIGH by forcing RERR HIGH. The receiver error circuit will signal a single ended zero when both D+ and D- are LOW by forcing RSE0 HIGH. A single ended zero is a valid state and is used to signal an end of packet (EOP) in signal transmission. (CAUTION: Since both RERR and RSE0 are CMOS outputs, care must be taken to ensure that RERR and RSE0 are NOT connected to V CC or GND.) The SP5301 has a suspend input pin (SUSPND) which enables a low power state while the USB bus is inactive. When SUSPND is asserted HIGH or SP5301 is in transmit mode (OE is LOW), the receive data pin (RCV) will be forced LOW. The SP5301 can transmit and receive serial data at both full speed, 12Mbps, and at low speed, 1.5Mbps, data rates. At full speed, the active supply current of the SP5301 is 6mA. In the suspend state, the supply current is typically 20nA. Full speed USB applications include ISDN, PBX, POTS, sampled analog devices, audio, printers, and telephony designs. Low speed USB applications include locator devices, keyboards, mouse, tablets, light pens, stylus, game peripherals, virtual reality peripherals, and monitor configurations. The USB protocol provides full support for the real-time data for voice, audio, and compressed video. The SP5301 is specifically geared towards low-cost USB solutions for the PC peripheral markets Waveforms 1 and 2 below show device behavior in transmit mode, at both low and full speed, with the D+/D- pins driving the load specified in figure 9. Waveform 1. D+/D- Transmit Mode, low speed Waveform 2. D+/D- Transmit Mode, full speed [ ] T T Ch1 500mV Ch2 500mV M 250nS Ch1 1.68 V 2 [ ] T T Ch1 500mV Ch2 500mV M 20.0nS Ch1 1.68 V 2 |
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