CY7C1460SV25

CY7C1462SV25

Document Number: 001-43804 Rev. *J

Page 9 of 31

Truth Table

Truth table for CY7C1460SV25/CY7C1462SV25 follows. [1, 2, 3, 4, 5, 6, 7]

Operation

DQ

Deselect Cycle

None

H

L

L

X

X

X

L

L–H

Tristate

Continue Deselect Cycle

None

X

L

H

X

X

X

L

L–H

Tristate

Read Cycle (Begin Burst)

External

L

L

L

H

X

L

L

L–H Data Out (Q)

Read Cycle (Continue Burst)

Next

X

L

H

X

X

L

L

L–H Data Out (Q)

NOP/Dummy Read (Begin Burst)

External

L

L

L

H

X

H

L

L–H

Tristate

Dummy Read (Continue Burst)

Next

X

L

H

X

X

H

L

L–H

Tristate

Write Cycle (Begin Burst)

External

L

L

L

L

L

X

L

L–H

Data In (D)

Write Cycle (Continue Burst)

Next

X

L

H

X

L

X

L

L–H

Data In (D)

NOP/WRITE ABORT (Begin Burst)

None

L

L

L

L

H

X

L

L–H

Tristate

WRITE ABORT (Continue Burst)

Next

X

L

H

X

H

X

L

L–H

Tristate

IGNORE CLOCK EDGE (Stall)

Current

X

L

X

X

X

X

H

L–H

–

Sleep MODE

None

X

H

X

XXXX

X

Tristate

Notes

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

3. When a write cycle is detected, all IOs are tristated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device powers up deselected and the IOs in a tristate condition, regardless of OE.