CY7C1460SV25

CY7C1462SV25

Document Number: 001-43804 Rev. *J

Page 7 of 31

Functional Overview

The

CY7C1460SV25/CY7C1462SV25

are

synchronous

pipelined Burst NoBL SRAMs designed specifically to eliminate

wait states during Write/Read transitions. All synchronous inputs

pass through input registers controlled by the rising edge of the

clock. The clock signal is qualified with the Clock Enable input

signal (CEN). If CEN is HIGH, the clock signal is not recognized

and all internal states are maintained. All synchronous

operations are qualified with CEN. All data outputs pass through

output registers controlled by the rising edge of the clock.

(250-MHz device).

Accesses can be initiated by asserting all three Chip Enables

Enable (CEN) is active LOW and ADV/LD is asserted LOW, the

address presented to the device is latched. The access can

either be a read or write operation, depending on the status of

operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

asynchronous Output Enable (OE) simplify depth expansion. All

operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW after the device has been

deselected to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core and

control logic. The control logic determines that a read access is

in progress and allows the requested data to propagate to the

input of the output register. At the rising edge of the next clock

the requested data is allowed to propagate through the output

register and on to the data bus within 2.6 ns (250-MHz device)

provided OE is active LOW. After the first clock of the read

access the output buffers are controlled by OE and the internal

control logic. OE must be driven LOW for the device to drive out

the requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initiated. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signals, its

output tristates following the next clock rise.

Burst Read Accesses

The CY7C1460SV25/CY7C1462SV25 have an on-chip burst

counter that allows the user the ability to supply a single address

and conduct up to four Reads without reasserting the address

inputs. ADV/LD must be driven LOW to load a new address into

the SRAM, as described in the Single Read Accesses section.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst mode,

a HIGH selects an interleaved burst sequence. Both burst

counters use A0 and A1 in the burst sequence, and wraps

around when incremented sufficiently. A HIGH input on ADV/LD

increments the internal burst counter regardless of the state of

chip enables inputs or WE. WE is latched at the beginning of a

burst cycle. Therefore, the type of access (Read or Write) is

maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are

asserted LOW. The address presented to the address inputs is

loaded into the Address Register. The write signals are latched

into the Control Logic block.

On the subsequent clock rise the data lines are automatically

tristated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

TCK

JTAG-Clock

Clock input to the JTAG Circuitry.

Power Supply Power supply inputs to the core of the device.

I/O Power

Supply

Power supply for the I/O circuitry.

Ground

Ground for the device. Should be connected to ground of the system.

NC

N/A

No Connects. This pin is not connected to the die.

NC/72M

N/A

Not connected to the Die. Can be tied to any voltage level.

NC/144M

N/A

Not connected to the Die. Can be tied to any voltage level.

NC/288M

N/A

Not connected to the Die. Can be tied to any voltage level.

NC/576M

N/A

Not connected to the Die. Can be tied to any voltage level.

NC/1G

N/A

Not Connected to the Die. Can be tied to any voltage level.

ZZ

Input-

Asynchronous

ZZ “sleep” Input. This active HIGH input places the device in a non time critical “sleep” condition

with data integrity preserved. During normal operation, this pin must be LOW or left floating.

ZZ pin has an internal pull down.

Pin Name

I/O Type

Pin Description