CY7C1371S datasheet(3/29 Pages) CYPRESS

Part #	CY7C1371S

Description	18-Mbit (512K 횞 36) Flow-Through SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1371S

Document Number: 001-43826 Rev. *F

Page 3 of 29

Contents

Pin Configurations ........................................................... 4

Pin Definitions .................................................................. 6

Functional Overview ........................................................ 7

Single Read Accesses ................................................ 7

Burst Read Accesses .................................................. 7

Single Write Accesses ................................................. 7

Burst Write Accesses .................................................. 8

Sleep Mode ................................................................. 8

Interleaved Burst Address Table ................................. 8

Linear Burst Address Table ......................................... 8

ZZ Mode Electrical Characteristics .............................. 8

Truth Table ........................................................................ 9

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10

Disabling the JTAG Feature ...................................... 10

Test Access Port (TAP) ............................................. 10

PERFORMING A TAP RESET .................................. 10

TAP REGISTERS ...................................................... 10

TAP Instruction Set ................................................... 10

TAP Controller State Diagram ....................................... 12

TAP Controller Block Diagram ...................................... 13

TAP Timing ...................................................................... 14

TAP AC Switching Characteristics ............................... 14

3.3 V TAP AC Test Conditions ....................................... 15

3.3 V TAP AC Output Load Equivalent ......................... 15

2.5 V TAP AC Test Conditions ....................................... 15

2.5 V TAP AC Output Load Equivalent ......................... 15

TAP DC Electrical Characteristics

and Operating Conditions ............................................. 15

Identification Register Definitions ................................ 16

Scan Register Sizes ....................................................... 16

Identification Codes ....................................................... 16

Boundary Scan Order .................................................... 17

Maximum Ratings ........................................................... 18

Operating Range ............................................................. 18

Electrical Characteristics ............................................... 18

Capacitance .................................................................... 19

Thermal Resistance ........................................................ 19

AC Test Loads and Waveforms ..................................... 19

Switching Characteristics .............................................. 20

Switching Waveforms .................................................... 21

Ordering Information ...................................................... 24

Ordering Code Definitions ......................................... 24

Package Diagrams .......................................................... 25

Acronyms ........................................................................ 27

Document Conventions ................................................. 27

Units of Measure ....................................................... 27

Document History Page ................................................. 28

Sales, Solutions, and Legal Information ...................... 29

Worldwide Sales and Design Support ....................... 29

Products .................................................................... 29

PSoC® Solutions ...................................................... 29

Cypress Developer Community ................................. 29

Technical Support ..................................................... 29

Similar Part No. - CY7C1371S

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1371B	876Kb / 26P	512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
	CY7C1371B-100AC	876Kb / 26P	512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
	CY7C1371B-100AI	876Kb / 26P	512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
	CY7C1371B-100BGC	876Kb / 26P	512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
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Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1371KV33	682Kb / 24P	18-Mbit (512K 횞 36/1M 횞 18) Flow-Through SRAM with NoBL??Architecture (With ECC)
	CY7C1461KV33	2Mb / 23P	36-Mbit (1M 횞 36/2M 횞 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1370KV25	2Mb / 30P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1371D	1,011Kb / 29P	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1371DV25	444Kb / 28P	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1371C	791Kb / 33P	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
	CY7C1461AV33	442Kb / 24P	36-Mbit (1 M 횞 36/2 M 횞 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1371D	1Mb / 37P	18-Mbit (512 K 횞 36/1 M 횞 18) Flow-Through SRAM with NoBL??Architecture
	CY7C1370KV33	999Kb / 32P	18-Mbit (512K 횞 36/1M 횞 18) Pipelined SRAM with NoBL??Architecture (With ECC)
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