SP3232EHET datasheet(10/19 Pages) SIPEX

Part #	SP3232EHET

Description	3.3V, 460 Kbps RS-232 Transceivers

Download	19 Pages

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Manufacturer	SIPEX [Sipex Corporation]

Direct Link	http://www.sipex.com

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10 / 19 page

Date: 06/22/04

SP3222EH/3232EH 3.3V, 460 Kbps RS-232 Transceivers

10

Receivers

The receivers convert EIA/TIA-232 levels to

TTL or CMOS logic output levels.

The

SP3222EH receivers have an inverting tri-state

output.Receiver outputs (RxOUT) are tri-stated

when the enable control EN = HIGH. In the

shutdown mode, the receivers can be active or

inactive. EN has no effect on TxOUT. The truth

table logic of the SP3222EH driver and receiver

outputs can be found in Table 2.

Since receiver input is usually from a transmis-

sion line where long cable lengths and system

interference can degrade the signal and inject

noise, the inputs have a typical hysteresis margin

of 300mV. Should an input be left unconnected,

a 5k

Ω pulldown resistor to ground forces the

output of the receiver HIGH.

Charge Pump

The Sipex patented charge pump (5,306,954)

uses a four–phase voltage shifting technique to

attain symmetrical 5.5V power supplies and

requires four external capacitors. The internal

power supply consists of a regulated dual charge

pump that provides an output voltage of 5.5V

regardless of the input voltage (V

CC) over the

+3.0V to +5.5V range.

In most circumstances, decoupling the power

supply can be achieved adequately using a

0.1

µF bypass capacitor at C5 (refer to Figures 6

and 7). In applications that are sensitive to

power-supply noise,V

CC and ground can be

decoupled with a capacitor of the same value

as charge-pump capacitor C1. It is always

important to physically locate bypass capacitors

close to the IC.

The charge pump operates in a discontinuous

mode using an internal oscillator. If the output

voltage is less than 5.5V, the charge pump is

enabled. If the output voltage exceeds 5.5V,

the charge pump is disabled. An oscillator

controls the four phases of the voltage shifting.

A description of each phase follows.

Phase 1: V

SS Charge Storage (Figure 12)

During this phase of the clock cycle, the positive

side of capacitors C

1 and C2 are charged to VCC.

C

l

+ is then switched to GND and the charge in

C

1

– is transferred to C

2

–. Since C

2

+ is connected

to V

CC, the voltage potential across capacitor C2

is now 2 times V

CC.

Phase 2: V

SS Transfer (Figure 13)

Phase two of the clock connects the negative

terminal of C

2 to the VSS storage capacitor and

the positive terminal of C

2 to GND.

This

transfers a negative generated voltage to C

3.

This generated voltage is regulated to a

minimum voltage of -5.5V. Simultaneous with

the transfer of the voltage to C

3, the positive side

of capacitor C

1 is switched to VCC and the

negative side is connected to GND.

Phase 3: V

DD Charge Storage (Figure 15)

The third phase of the clock is identical to the

first phase — the charge transferred in C

1

produces –V

CC in the negative terminal of C1,

which is applied to the negative side of capacitor

C

2.

Since C

2

+ is at V

CC, the voltage potential

across C

2 is 2 times VCC.

Table 2. Truth Table Logic for Shutdown and Enable

Control

N

D

H

SN

ET

U

O

x

TT

U

O

x

R

00

e

t

a

t

s

-

i

r

Te

v

i

t

c

A

01

e

t

a

t

s

-

i

r

Te

t

a

t

s

-

i

r

T

10

e

v

i

t

c

Ae

v

i

t

c

A

11

e

v

i

t

c

Ae

t

a

t

s

-

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T

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