OVP

UVP

PRE-BIASED

STARTUP

DISABLE

0.6V

LM21215A

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SNOSB87C – MARCH 2011 – REVISED JANUARY 2016

Feature Description (continued)

As shown above, the soft-start capacitance is set by the nominal feedback voltage level 0.6 V, the soft-start

defaults to a soft-start time of 500 µs. The LM21215A cannot startup faster than 500 µs. When Enable is cycled

or the device enters UVLO, the soft-start capacitor is discharged to reset the startup process. This also occurs

when the device enters short circuit mode following an overcurrent event.

7.3.4 PGOOD Indicator

The PGOOD flag provides the user with a way to monitor the status of the LM21215A. In order to use the

PGOOD function, the application must provide a pullup resistor to a desired DC voltage, for example VIN.

PGOOD responds to a fault condition by pulling PGOOD low with the open-drain output. PGOOD pulls low on

12

μs and 15 μs of built-in deglitch time for rising and falling edges, respectively.

Figure 24 shows the conditions that cause PGOOD to respond.

Figure 24. PGOOD Indicator Operation

7.3.5 Frequency Synchronization

The SYNC pin allows the LM21215A to be synchronized to an external clock frequency. When a clock signal

within the allowable frequency range of 300 kHz to 1.5 MHz is present on SYNC, an internal PLL synchronizes

the turn-on of the high-side MOSFET (SW voltage rising) to the negative edge of the clock signal, as seen in

Figure 25.

The clock signal can be present on the SYNC pin before the device is powered on without loading of the clock

signal. Alternatively, if a clock signal is not present while the device is powered up, the default switching

frequency is 500 kHz. Once the clock signal is available, the device synchronizes to the clock frequency. The

time required to achieve synchronization depends on the clock frequency.

Copyright © 2011–2016, Texas Instruments Incorporated

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