LM21215A

SNOSB87C – MARCH 2011 – REVISED JANUARY 2016

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10 Layout

10.1 Layout Guidelines

PC board layout is an important and critical part of any DC-DC converter design. The performance of any

switching converter depends as much upon the layout of the PCB as the component selection. Poor layout

disrupts the performance of a switching converter and surrounding circuitry by contributing to EMI, ground

bounce, conduction loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter,

possibly resulting in poor regulation or instability. There are several paths that conduct high slew-rate currents or

voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade

the power-supply performance.

The following guidelines serve to help users to design a PCB with the best power conversion performance,

thermal performance, and minimized generation of unwanted EMI.

1. Locate the input capacitors as close as possible to the PVIN and PGND pins, and place the inductor as close

as possible to the SW pins and output capacitors. As described further in the Compact PCB Layout for EMI

Reduction section, this placement is to minimize the area of switching current loops and reduce the resistive

loss of the high current path. Ideally, use a ground plane on the top layer that connects the PGND pins, the

exposed pad of the device, and the return terminals of the input and output capacitors in a small area near

pins 10 and 11 of the device. For more details, refer to the board layout detailed in application note AN-2131

LM21215A Evaluation Board, SNVA477.

2. Minimize the copper area of the switch node. Route the six SW pins on a single top-layer plane to the

inductor terminal using a wide trace to minimize conduction loss. The inductor can be placed on the bottom

side of the PCB relative to the LM21215A, but take care to avoid any coupling of the inductor's magnetic field

to sensitive feedback or compensation traces.

3. Use a solid ground plane on layer two of the PCB, particularly underneath the LM21215A and power stage

components. This plane functions as a noise shield and also as a heat dissipation path.

4. Make input and output power bus connections as wide and short as possible to reduce voltage drops on the

input and output of the converter and to improve efficiency. Use copper planes on top to connect the multiple

PVIN pins and PGND pins together.

5. Provide enough PCB area for proper heat-sinking. As stated in the Thermal Design section, use enough

Make the top and bottom PCB layers with two ounce copper thickness and no less than one ounce. Use an

array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the

PCB has multiple copper layers as recommended, connect these thermal vias to the inner layer heat-

spreading ground planes.

6. Route the sense trace from the VOUT point of regulation to the feedback resistors away from the SW pins

and inductor to avoid contaminating this feedback signal with switching noise. This routing is most important

when high resistances are used to set the output voltage. Routing the feedback trace on a different layer

than the inductor and SW node trace is recommended such that a ground plane exists between the sense

trace and inductor or SW node polygon to provide further cancellation of EMI on the feedback trace.

7. If voltage accuracy at the load is important, ensure that the feedback voltage sense is made directly at the

load terminals. Doing so corrects for voltage drops in the PCB planes and traces and provides optimal output

voltage setpoint accuracy and load regulation. Place the feedback resistor divider closer to the FB node,

rather than close to the load, because the FB node is the input to the error amplifier and is thus noise

sensitive. COMP is a also noise-sensitive node and the compensation components must be located as close

as possible to the device.

8. Place the AVIN bypass capacitor and the soft-start capacitor close to their respective pins.

9. See Related Documentation for additional important guidelines.

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