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LM21215AMHE-1 Datasheet(PDF) 23 Page - Texas Instruments

Part No. LM21215AMHE-1
Description  15-A Ultra High-Efficiency Synchronous Buck Converter
Download  38 Pages
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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LM21215AMHE-1 Datasheet(HTML) 23 Page - Texas Instruments

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LC
Z1
C1
C1
Z2
LC
C1
FB1
C3
P1
ESR
C2
C3
SW
C1
C2
P2
C1
C1
C2
f
1
f
2
2
R
C
1
f
f
2
R
R
C
1
f
f
2
R
C
F
C
C
f
2
2
R
C
C
˜ S ˜
˜
˜ S ˜
˜
˜ S ˜
˜
˜ S ˜
˜
˜
100
1k
10k
100k
1M
10M
-20
0
20
40
60
80
100
-180
-135
-90
-45
0
45
90
FREQUENCY (Hz)
GAIN
PHASE
LM21215A
www.ti.com
SNOSB87C – MARCH 2011 – REVISED JANUARY 2016
The pole located at the origin gives high open-loop gain at DC, translating into improved load regulation
accuracy. This pole occurs at a very low frequency due to the finite gain of the error amplifier; however, its
location is approximated at DC for the purposes of compensation. The other two poles and two zeros are located
accordingly to stabilize the voltage-mode loop depending on the power stage complex poles and their quality
factor, Q. Figure 34 illustrates a typical type-III compensator transfer function.
Figure 34. Type-III Compensation Network Bode Plot
As seen in Figure 34, the two compensator zeros located at (fLC/2, fLC) provide a phase boost. This mitigates the
effect of the phase loss from the output filter. The compensation network also adds two poles to the system. One
pole is located at the output capacitor ESR zero (fESR) and the other pole is at half the switching frequency
(FSW/2) to roll off the high frequency response.
The dependency of the pole and zero locations on the compensation components is described as follows:
The output capacitance, COUT, depends on capacitor chemistry and bias voltage. For multi-layer ceramic
capacitors (MLCC), the total capacitance degrades as the DC bias voltage is increased. To accurately calculate
and optimize the compensation network, it is advisable to determine the effective capacitance of the output
capacitors when biased at the output voltage.
The example given here is the total output capacitance using three MLCC output capacitors biased at 1.2 V, as
seen in the typical application schematic of Figure 28. 50% capacitance derating is assumed.
NOTE
It is more conservative, from a stability standpoint, to err on the side of a lower output
capacitance in the compensation calculations rather than a higher, as this will result in a
lower bandwidth but increased phase margin.
Copyright © 2011–2016, Texas Instruments Incorporated
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Product Folder Links: LM21215A


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