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LM21215A Datasheet(PDF) 30 Page - Texas Instruments |
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LM21215A Datasheet(HTML) 30 Page - Texas Instruments |
30 / 38 page LM21215A-1 EVALUATION MODULE LM21215A SNOSB87C – MARCH 2011 – REVISED JANUARY 2016 www.ti.com Layout Guidelines (continued) High ambient temperatures and large values of RθJA reduce the maximum available output current. If the junction temperature exceeds 165°C, the LM21215A cycles in and out of thermal shutdown. Thermal shutdown may be a sign of inadequate heat-sinking or excessive power dissipation. Improve PCB heat-sinking by using more thermal vias, a larger board, or more heat-spreading layers within that board. As stated in application note Semiconductor and IC Package Thermal Metrics, SPRA953, the values given in the Thermal Information table are not always valid for design purposes to estimate the thermal performance of the application. The values reported in the Thermal Information table are measured under a specific set of conditions that are seldom obtained in an actual application. The effective RθJA is a critical parameter and depends on many factors (such as power dissipation, air temperature, PCB area, copper heat-sink area, number of thermal vias under the package, air flow, and adjacent component placement). The LM21215A uses an advanced flip-chip-on- lead (FCOL) package and its exposed pad has a direct electrical and thermal connection to PGND. This pad must be soldered directly to the PCB copper ground plane to provide an effective heat-sink and proper electrical connection. Use the documents listed in Related Documentation as a guide for optimized thermal PCB design and estimating RθJA for a given application environment. 10.1.3 Ground Plane Design As mentioned previously, using one of the middle layers as a solid ground plane is recommended. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground plane using an array of vias under the exposed pad. The PGND pins are connected to the source of the integrated low-side power MOSFET. Connect these pins directly to the return terminals of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce because of load current variations. The PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and is ideal for sensitive routes. 10.2 Layout Example Figure 42. Layout Example Showing Top Layer Copper and Silkscreen 30 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM21215A |
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